From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6318FEE0219 for ; Wed, 11 Sep 2024 08:51:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soJ3H-0007mq-6q; Wed, 11 Sep 2024 04:50:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soJ3E-0007jb-Dy; Wed, 11 Sep 2024 04:50:12 -0400 Received: from mta-04.yadro.com ([89.207.88.248]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soJ3B-0001SK-9H; Wed, 11 Sep 2024 04:50:11 -0400 DKIM-Filter: OpenDKIM Filter v2.11.0 mta-04.yadro.com 25CABC000E DKIM-Signature: v=1; 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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: T-EXCH-10.corp.yadro.com (172.17.11.60) To T-EXCH-12.corp.yadro.com (172.17.11.143) Received-SPF: permerror client-ip=89.207.88.248; envelope-from=alexei.filippov@syntacore.com; helo=mta-04.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 08.07.2024 16:42, Philippe Mathieu-Daudé wrote: > Hi Aleksei, > > On 8/7/24 11:46, Aleksei Filippov wrote: >> On 25.06.2024 21:18, Richard Henderson wrote: >>> On 6/25/24 07:46, Alexei Filippov wrote: >>>> Was added call backs for machine specific pmu events. >>>> Simplify monitor functions by adding new hash table, which going to map >>>> counter number and event index. >>>> Was added read/write callbacks which going to simplify support for events, >>>> which expected to have different behavior. >>>> >>>> Signed-off-by: Alexei Filippov >>>> --- >>>> Changes since v2: >>>>         -rebased to latest master >>>>   target/riscv/cpu.h |   9 +++ >>>>   target/riscv/csr.c |  43 +++++++++----- >>>>   target/riscv/pmu.c | 139 ++++++++++++++++++++++----------------------- >>>>   target/riscv/pmu.h |  11 ++-- >>>>   4 files changed, 115 insertions(+), 87 deletions(-) >>>> >>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >>>> index 6fe0d712b4..fbf82b050b 100644 >>>> --- a/target/riscv/cpu.h >>>> +++ b/target/riscv/cpu.h >>>> @@ -374,6 +374,13 @@ struct CPUArchState { >>>>       uint64_t (*rdtime_fn)(void *); >>>>       void *rdtime_fn_arg; >>>> +    /*machine specific pmu callback */ >>>> +    void (*pmu_ctr_write)(PMUCTRState *counter, uint32_t event_idx, >>>> +                          target_ulong val, bool high_half); >>>> +    target_ulong (*pmu_ctr_read)(PMUCTRState *counter, uint32_t event_idx, >>>> +                                 bool high_half); >>>> +    bool (*pmu_vendor_support)(uint32_t event_idx); >>> >>> Do these really belong in CPUArchState, rather than RISCVCPUClass? >>> >>> Surely there's more to this series, since these fields are never set... >>> >>> >>> r~ >> >> Initially this callbacks was added to CPUArchState just to be along with >> similar implementation with rdtime_fn*. >> >> Yes, you're right, there are more series to this, but, it can't be separated >> from syntacore specific parts, which is unfortunately not ready yet to be >> published. So, I can prepare second patch to implement PMU subsystem for virt >> device. What do you think about it? (I'll send it in the few days). > > How can we test your patch meanwhile? Sorry for such late response, but anyway, I created an RFC with PoC and description on how I tested this and resend patch with PoC all together. https://lore.kernel.org/all/20240910174747.148141-1-alexei.filippov@syntacore.com/ > > Thanks, > > Phil. > -- Sincerely, Aleksei Filippov