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From: Paolo Bonzini <pbonzini@redhat.com>
To: P J P <ppandit@redhat.com>, Qemu Developers <qemu-devel@nongnu.org>
Cc: Niu Guoxiang <niuguoxiang@huawei.com>,
	Prasad J Pandit <pjp@fedoraproject.org>
Subject: Re: [Qemu-devel] [PATCH] pc: restrict port92 register value to 2 bits
Date: Thu, 2 Nov 2017 10:37:47 +0100	[thread overview]
Message-ID: <f96b7ffe-83d3-f328-cf74-e05a0acb65ec@redhat.com> (raw)
In-Reply-To: <20171102093625.32342-1-ppandit@redhat.com>

On 02/11/2017 10:36, P J P wrote:
> From: Prasad J Pandit <pjp@fedoraproject.org>
> 
> Port 92 configuration register holds an 8-bit value. Of 8-bits,
> bits 0-1 are used and 2-7 are reserved. Restrict the supplied
> value to 2 bits.

This patch is not necessary.  "Do nothing and just report back the value
that was written" is an okay implementation of reserved bits.

Paolo


> Reported-by: Niu Guoxiang <niuguoxiang@huawei.com>
> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
> ---
>  hw/i386/pc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 05985d4927..883384a599 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -515,6 +515,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val,
>      Port92State *s = opaque;
>      int oldval = s->outport;
>  
> +    val &= 0x03;
>      DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
>      s->outport = val;
>      qemu_set_irq(s->a20_out, (val >> 1) & 1);
> 

  reply	other threads:[~2017-11-02  9:37 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-02  9:36 [Qemu-devel] [PATCH] pc: restrict port92 register value to 2 bits P J P
2017-11-02  9:37 ` Paolo Bonzini [this message]
2017-11-02 12:25   ` Philippe Mathieu-Daudé

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