From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "mst@redhat.com" <mst@redhat.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"richard.henderson@linaro.org" <richard.henderson@linaro.org>,
"eduardo@habkost.net" <eduardo@habkost.net>,
"peterx@redhat.com" <peterx@redhat.com>,
"david@redhat.com" <david@redhat.com>,
"philmd@linaro.org" <philmd@linaro.org>,
"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"imammedo@redhat.com" <imammedo@redhat.com>,
"anisinha@redhat.com" <anisinha@redhat.com>,
"vasant.hegde@amd.com" <vasant.hegde@amd.com>,
"suravee.suthikulpanit@amd.com" <suravee.suthikulpanit@amd.com>,
"santosh.shukla@amd.com" <santosh.shukla@amd.com>,
"sarunkod@amd.com" <sarunkod@amd.com>,
"Wei.Huang2@amd.com" <Wei.Huang2@amd.com>,
"Ankit.Soni@amd.com" <Ankit.Soni@amd.com>,
Ethan MILON <pre_ethan.milon@eviden.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"boris.ostrovsky@oracle.com" <boris.ostrovsky@oracle.com>
Subject: Re: [PATCH v3 21/22] i386/intel-iommu: Move dma_translation to x86-iommu
Date: Mon, 22 Sep 2025 05:33:36 +0000 [thread overview]
Message-ID: <f97bc435e8ed1c295919350d300068e45ab0bb67.camel@eviden.com> (raw)
In-Reply-To: <20250919213515.917111-22-alejandro.j.jimenez@oracle.com>
On Fri, 2025-09-19 at 21:35 +0000, Alejandro Jimenez wrote:
> From: Joao Martins <[joao.m.martins@oracle.com](mailto:joao.m.martins@oracle.com)>
>
> To be later reused by AMD, now that it shares similar property.
>
> Signed-off-by: Joao Martins <[joao.m.martins@oracle.com](mailto:joao.m.martins@oracle.com)>
> Signed-off-by: Alejandro Jimenez <[alejandro.j.jimenez@oracle.com](mailto:alejandro.j.jimenez@oracle.com)>
Hi Alejandro,
Most commits messages for the Intel IOMMU are formatted like "intel_iommu: XYZ".
We should probably stick to that.
Otherwise, the change looks good to me.
Thanks
cmd
> ---
> hw/i386/intel_iommu.c | 5 ++---
> hw/i386/x86-iommu.c | 1 +
> include/hw/i386/x86-iommu.h | 1 +
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 83c5e444131a3..2b848d094cfb7 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2701,7 +2701,7 @@ static void vtd_handle_gcmd_write(IntelIOMMUState *s)
> uint32_t changed = status ^ val;
>
> trace_vtd_reg_write_gcmd(status, val);
> - if ((changed & VTD_GCMD_TE) && s->dma_translation) {
> + if ((changed & VTD_GCMD_TE) && x86_iommu->dma_translation) {
> /* Translation enable/disable */
> vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
> }
> @@ -3835,7 +3835,6 @@ static const Property vtd_properties[] = {
> DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
> DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
> DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
> - DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, true),
> DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false),
> DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true),
> };
> @@ -4553,7 +4552,7 @@ static void vtd_cap_init(IntelIOMMUState *s)
> if (s->dma_drain) {
> s->cap |= VTD_CAP_DRAIN;
> }
> - if (s->dma_translation) {
> + if (x86_iommu->dma_translation) {
> if (s->aw_bits >= VTD_HOST_AW_39BIT) {
> s->cap |= VTD_CAP_SAGAW_39bit;
> }
> diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c
> index d34a6849f4ae9..c127a44bb4bc8 100644
> --- a/hw/i386/x86-iommu.c
> +++ b/hw/i386/x86-iommu.c
> @@ -130,6 +130,7 @@ static const Property x86_iommu_properties[] = {
> intr_supported, ON_OFF_AUTO_AUTO),
> DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false),
> DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true),
> + DEFINE_PROP_BOOL("dma-translation", X86IOMMUState, dma_translation, true),
> };
>
> static void x86_iommu_class_init(ObjectClass *klass, const void *data)
> diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h
> index bfd21649d0838..e89f55a5c215c 100644
> --- a/include/hw/i386/x86-iommu.h
> +++ b/include/hw/i386/x86-iommu.h
> @@ -64,6 +64,7 @@ struct X86IOMMUState {
> OnOffAuto intr_supported; /* Whether vIOMMU supports IR */
> bool dt_supported; /* Whether vIOMMU supports DT */
> bool pt_supported; /* Whether vIOMMU supports pass-through */
> + bool dma_translation; /* Whether vIOMMU supports DMA translation */
> QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
> };
>
next prev parent reply other threads:[~2025-09-22 5:34 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-19 21:34 [PATCH v3 00/22] AMD vIOMMU: DMA remapping support for VFIO devices Alejandro Jimenez
2025-09-19 21:34 ` [PATCH v3 01/22] memory: Adjust event ranges to fit within notifier boundaries Alejandro Jimenez
2025-09-19 21:34 ` [PATCH v3 02/22] amd_iommu: Document '-device amd-iommu' common options Alejandro Jimenez
2025-09-19 21:34 ` [PATCH v3 03/22] amd_iommu: Reorder device and page table helpers Alejandro Jimenez
2025-09-19 21:34 ` [PATCH v3 04/22] amd_iommu: Helper to decode size of page invalidation command Alejandro Jimenez
2025-09-19 21:34 ` [PATCH v3 05/22] amd_iommu: Add helper function to extract the DTE Alejandro Jimenez
2025-09-19 21:34 ` [PATCH v3 06/22] amd_iommu: Return an error when unable to read PTE from guest memory Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 07/22] amd_iommu: Add helpers to walk AMD v1 Page Table format Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 08/22] amd_iommu: Add a page walker to sync shadow page tables on invalidation Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 09/22] amd_iommu: Add basic structure to support IOMMU notifier updates Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 10/22] amd_iommu: Sync shadow page tables on page invalidation Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 11/22] amd_iommu: Use iova_tree records to determine large page size on UNMAP Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 12/22] amd_iommu: Unmap all address spaces under the AMD IOMMU on reset Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 13/22] amd_iommu: Add replay callback Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 14/22] amd_iommu: Invalidate address translations on INVALIDATE_IOMMU_ALL Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 15/22] amd_iommu: Toggle memory regions based on address translation mode Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 16/22] amd_iommu: Set all address spaces to use passthrough mode on reset Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 17/22] amd_iommu: Add dma-remap property to AMD vIOMMU device Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 18/22] amd_iommu: Toggle address translation mode on devtab entry invalidation Alejandro Jimenez
2025-10-06 6:08 ` Sairaj Kodilkar
2025-10-06 6:15 ` Michael S. Tsirkin
2025-10-06 6:25 ` Sairaj Kodilkar
2025-10-06 16:03 ` Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 19/22] amd_iommu: Do not assume passthrough translation when DTE[TV]=0 Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 20/22] amd_iommu: Refactor amdvi_page_walk() to use common code for page walk Alejandro Jimenez
2025-09-19 21:35 ` [PATCH v3 21/22] i386/intel-iommu: Move dma_translation to x86-iommu Alejandro Jimenez
2025-09-22 5:33 ` CLEMENT MATHIEU--DRIF [this message]
2025-09-19 21:35 ` [PATCH v3 22/22] amd_iommu: HATDis/HATS=11 support Alejandro Jimenez
2025-10-06 16:07 ` [PATCH v3 00/22] AMD vIOMMU: DMA remapping support for VFIO devices Cédric Le Goater
2025-10-06 18:44 ` Alejandro Jimenez
2025-10-07 5:45 ` Cédric Le Goater
2025-10-07 8:17 ` Vasant Hegde
2025-10-07 19:04 ` Joao Martins
2025-10-07 20:41 ` Cédric Le Goater
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