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[88.21.202.78]) by smtp.gmail.com with ESMTPSA id i2sm7005292wmb.28.2020.02.11.22.40.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Feb 2020 22:40:56 -0800 (PST) Subject: Re: [PATCH 04/13] target/arm: Factor out PMU register definitions To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200211173726.22541-1-peter.maydell@linaro.org> <20200211173726.22541-5-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 12 Feb 2020 07:40:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200211173726.22541-5-peter.maydell@linaro.org> Content-Language: en-US X-MC-Unique: UdK42eohN9OC46bl4e7TQA-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/11/20 6:37 PM, Peter Maydell wrote: > Pull the code that defines the various PMU registers out > into its own function, matching the pattern we have > already for the debug registers. >=20 > Apart from one style fix to a multi-line comment, this > is purely movement of code with no changes to it. >=20 > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 158 +++++++++++++++++++++++--------------------- > 1 file changed, 82 insertions(+), 76 deletions(-) >=20 > diff --git a/target/arm/helper.c b/target/arm/helper.c > index bf083c369fc..0011a22f42d 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -5822,6 +5822,87 @@ static void define_debug_regs(ARMCPU *cpu) > } > } > =20 > +static void define_pmu_regs(ARMCPU *cpu) > +{ > + /* > + * v7 performance monitor control register: same implementor > + * field as main ID register, and we implement four counters in > + * addition to the cycle count register. > + */ > + unsigned int i, pmcrn =3D 4; > + ARMCPRegInfo pmcr =3D { > + .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D= 0, .opc2 =3D 0, > + .access =3D PL0_RW, > + .type =3D ARM_CP_IO | ARM_CP_ALIAS, > + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), > + .accessfn =3D pmreg_access, .writefn =3D pmcr_write, > + .raw_writefn =3D raw_write, > + }; > + ARMCPRegInfo pmcr64 =3D { > + .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, > + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, > + .access =3D PL0_RW, .accessfn =3D pmreg_access, > + .type =3D ARM_CP_IO, > + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), > + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT= ), > + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, > + }; > + define_one_arm_cp_reg(cpu, &pmcr); > + define_one_arm_cp_reg(cpu, &pmcr64); > + for (i =3D 0; i < pmcrn; i++) { > + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); > + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", i)= ; > + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); > + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0", = i); > + ARMCPRegInfo pmev_regs[] =3D { > + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, > + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, > + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, > + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn= , > + .accessfn =3D pmreg_access }, > + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, > + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (= i >> 3)), > + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_a= ccess, > + .type =3D ARM_CP_IO, > + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn= , > + .raw_readfn =3D pmevcntr_rawread, > + .raw_writefn =3D pmevcntr_rawwrite }, > + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, > + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7= , > + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, > + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_write= fn, > + .accessfn =3D pmreg_access }, > + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64= , > + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & = (i >> 3)), > + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_a= ccess, > + .type =3D ARM_CP_IO, > + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_write= fn, > + .raw_writefn =3D pmevtyper_rawwrite }, > + REGINFO_SENTINEL > + }; > + define_arm_cp_regs(cpu, pmev_regs); > + g_free(pmevcntr_name); > + g_free(pmevcntr_el0_name); > + g_free(pmevtyper_name); > + g_free(pmevtyper_el0_name); > + } > + if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && > + FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { > + ARMCPRegInfo v81_pmu_regs[] =3D { > + { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, > + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 = =3D 4, > + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D A= RM_CP_CONST, > + .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, > + { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, > + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 = =3D 5, > + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D A= RM_CP_CONST, > + .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, > + REGINFO_SENTINEL > + }; > + define_arm_cp_regs(cpu, v81_pmu_regs); > + } > +} > + > /* We don't know until after realize whether there's a GICv3 > * attached, and that is what registers the gicv3 sysregs. > * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PF= R0_EL1 > @@ -6244,67 +6325,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) > define_arm_cp_regs(cpu, pmovsset_cp_reginfo); > } > if (arm_feature(env, ARM_FEATURE_V7)) { > - /* v7 performance monitor control register: same implementor > - * field as main ID register, and we implement four counters in > - * addition to the cycle count register. > - */ > - unsigned int i, pmcrn =3D 4; > - ARMCPRegInfo pmcr =3D { > - .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1= =3D 0, .opc2 =3D 0, > - .access =3D PL0_RW, > - .type =3D ARM_CP_IO | ARM_CP_ALIAS, > - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), > - .accessfn =3D pmreg_access, .writefn =3D pmcr_write, > - .raw_writefn =3D raw_write, > - }; > - ARMCPRegInfo pmcr64 =3D { > - .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, > - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 0, > - .access =3D PL0_RW, .accessfn =3D pmreg_access, > - .type =3D ARM_CP_IO, > - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), > - .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_S= HIFT), > - .writefn =3D pmcr_write, .raw_writefn =3D raw_write, > - }; > - define_one_arm_cp_reg(cpu, &pmcr); > - define_one_arm_cp_reg(cpu, &pmcr64); > - for (i =3D 0; i < pmcrn; i++) { > - char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); > - char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0"= , i); > - char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); > - char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL= 0", i); > - ARMCPRegInfo pmev_regs[] =3D { > - { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, > - .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i = & 7, > - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS= , > - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_wri= tefn, > - .accessfn =3D pmreg_access }, > - { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_A= A64, > - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3= & (i >> 3)), > - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmr= eg_access, > - .type =3D ARM_CP_IO, > - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_wri= tefn, > - .raw_readfn =3D pmevcntr_rawread, > - .raw_writefn =3D pmevcntr_rawwrite }, > - { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, > - .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i= & 7, > - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS= , > - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_w= ritefn, > - .accessfn =3D pmreg_access }, > - { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_= AA64, > - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (= 3 & (i >> 3)), > - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmr= eg_access, > - .type =3D ARM_CP_IO, > - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_w= ritefn, > - .raw_writefn =3D pmevtyper_rawwrite }, > - REGINFO_SENTINEL > - }; > - define_arm_cp_regs(cpu, pmev_regs); > - g_free(pmevcntr_name); > - g_free(pmevcntr_el0_name); > - g_free(pmevtyper_name); > - g_free(pmevtyper_el0_name); TIL git-diff --color-moved Maybe move PERFMON block first, then extract define_pmu_regs()? In any case, Reviewed-by: Philippe Mathieu-Daud=C3=A9 > - } > ARMCPRegInfo clidr =3D { > .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, > .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D= 1, > @@ -6315,24 +6335,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) > define_one_arm_cp_reg(cpu, &clidr); > define_arm_cp_regs(cpu, v7_cp_reginfo); > define_debug_regs(cpu); > + define_pmu_regs(cpu); > } else { > define_arm_cp_regs(cpu, not_v7_cp_reginfo); > } > - if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && > - FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { > - ARMCPRegInfo v81_pmu_regs[] =3D { > - { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, > - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 = =3D 4, > - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D A= RM_CP_CONST, > - .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, > - { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, > - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 = =3D 5, > - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D A= RM_CP_CONST, > - .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, > - REGINFO_SENTINEL > - }; > - define_arm_cp_regs(cpu, v81_pmu_regs); > - } > if (arm_feature(env, ARM_FEATURE_V8)) { > /* AArch64 ID registers, which all have impdef reset values. > * Note that within the ID register ranges the unused slots >=20