From: Richard Henderson <richard.henderson@linaro.org>
To: Jan Bobek <jan.bobek@gmail.com>, qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [RISU RFC PATCH v1 4/7] risugen_x86: add module
Date: Sat, 29 Jun 2019 14:03:23 +0200 [thread overview]
Message-ID: <fa3776c7-5b82-0fb5-c151-0946e7b90a1b@linaro.org> (raw)
In-Reply-To: <58987aa3-7b8b-0ef7-741a-2c0b79943fe7@gmail.com>
On 6/28/19 7:06 PM, Jan Bobek wrote:
> That's true. (Although not in all cases; see Table 2-5 in the Intel Manual,
> Volume 2, Chapter 2, Section 2.2.1 "REX Prefixes" for some cases when REX.B
> is not decoded.) This is a compromise that I've accepted, at least for v1
> of the patch series. Note that this problem is also present in config entries
> such as
>
> PMOVMSKB SSE 00001111 11010111 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); }
>
> Here, we force MODRM.REG != 4, but this avoids not only ESP/RSP, but
> also R12.
>
> Hmmm... I suppose I have some ideas on how to do it better. I'll try
> to fix this, though I suspect getting it 100 % right might be
> difficult and time-consuming.
I wonder if it might be better to do the randomization at a higher level:
* Pick full registers, either 3 bits for 32-bit or 4 bits for 64-bit,
and eventually 5 bits for avx512 z-regs for evex encoding. Let
risugen_x86_asm encode those depending on the chosen encoding.
* Pick only register vs memory for MODRM.MOD. If memory, randomize
base + index + shift + disp. Let risugen_x86_asm encode those
values into the modrm+sib+offset.
r~
next prev parent reply other threads:[~2019-06-29 12:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-19 5:04 [Qemu-devel] [RISU RFC PATCH v1 0/7] Support for generating x86 SSE/SSE2 test images Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 1/7] risugen_common: add insnv, randint_constr, rand_fill Jan Bobek
2019-06-27 8:53 ` Richard Henderson
2019-06-28 15:10 ` Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 2/7] risugen_x86_asm: add module Jan Bobek
2019-06-27 9:05 ` Richard Henderson
2019-06-28 15:57 ` Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 3/7] risugen_x86_emit: " Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 4/7] risugen_x86: " Jan Bobek
2019-06-27 10:29 ` Richard Henderson
2019-06-27 10:53 ` Richard Henderson
2019-06-28 16:03 ` Jan Bobek
2019-06-28 17:06 ` Jan Bobek
2019-06-29 12:03 ` Richard Henderson [this message]
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 5/7] risugen: allow all byte-aligned instructions Jan Bobek
2019-06-27 10:30 ` Richard Henderson
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 6/7] x86.risu: add SSE instructions Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 7/7] x86.risu: add SSE2 instructions Jan Bobek
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