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[93.34.153.63]) by smtp.gmail.com with ESMTPSA id c1sm9860084wrh.1.2019.06.29.05.03.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Jun 2019 05:03:25 -0700 (PDT) To: Jan Bobek , qemu-devel@nongnu.org References: <20190619050447.22201-1-jan.bobek@gmail.com> <20190619050447.22201-5-jan.bobek@gmail.com> <58987aa3-7b8b-0ef7-741a-2c0b79943fe7@gmail.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: Date: Sat, 29 Jun 2019 14:03:23 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <58987aa3-7b8b-0ef7-741a-2c0b79943fe7@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: Re: [Qemu-devel] [RISU RFC PATCH v1 4/7] risugen_x86: add module X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/28/19 7:06 PM, Jan Bobek wrote: > That's true. (Although not in all cases; see Table 2-5 in the Intel Manual, > Volume 2, Chapter 2, Section 2.2.1 "REX Prefixes" for some cases when REX.B > is not decoded.) This is a compromise that I've accepted, at least for v1 > of the patch series. Note that this problem is also present in config entries > such as > > PMOVMSKB SSE 00001111 11010111 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); } > > Here, we force MODRM.REG != 4, but this avoids not only ESP/RSP, but > also R12. > > Hmmm... I suppose I have some ideas on how to do it better. I'll try > to fix this, though I suspect getting it 100 % right might be > difficult and time-consuming. I wonder if it might be better to do the randomization at a higher level: * Pick full registers, either 3 bits for 32-bit or 4 bits for 64-bit, and eventually 5 bits for avx512 z-regs for evex encoding. Let risugen_x86_asm encode those depending on the chosen encoding. * Pick only register vs memory for MODRM.MOD. If memory, randomize base + index + shift + disp. Let risugen_x86_asm encode those values into the modrm+sib+offset. r~