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([2804:431:c7c6:bec1:d9bb:8ce0:5ce7:a377]) by smtp.gmail.com with ESMTPSA id o6-20020a4a2c06000000b0031c0514194fsm1048479ooo.31.2022.02.25.05.44.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Feb 2022 05:44:23 -0800 (PST) Message-ID: Date: Fri, 25 Feb 2022 10:44:20 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 02/18] ppc/xive2: Introduce a presenter matching routine Content-Language: en-US To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20211126115349.2737605-1-clg@kaod.org> <20211126115349.2737605-3-clg@kaod.org> From: Daniel Henrique Barboza In-Reply-To: <20211126115349.2737605-3-clg@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::335 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Frederic Barrat , Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/26/21 08:53, Cédric Le Goater wrote: > The VP space is larger in XIVE2 (P10), 24 bits instead of 19bits on > XIVE (P9), and the CAM line can use a 7bits or 8bits thread id. > > For now, we only use 7bits thread ids, same as P9, but because of the > change of the size of the VP space, the CAM matching routine is > different between P9 and P10. It is easier to duplicate the whole > routine than to add extra handlers in xive_presenter_tctx_match() used > for P9. > > We might come with a better solution later on, after we have added > some more support for the XIVE2 controller. > > Signed-off-by: Cédric Le Goater > --- Reviewed-by: Daniel Henrique Barboza > include/hw/ppc/xive2.h | 9 +++++ > hw/intc/xive2.c | 82 ++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 91 insertions(+) > > diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h > index a3cd02520475..e881c039d9c0 100644 > --- a/include/hw/ppc/xive2.h > +++ b/include/hw/ppc/xive2.h > @@ -55,6 +55,15 @@ int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, > > void xive2_router_notify(XiveNotifier *xn, uint32_t lisn); > > +/* > + * XIVE2 Presenter (POWER10) > + */ > + > +int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, > + uint8_t format, > + uint8_t nvt_blk, uint32_t nvt_idx, > + bool cam_ignore, uint32_t logic_serv); > + > /* > * XIVE2 END ESBs (POWER10) > */ > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index e4aa614f3cc8..9e186bbb6cd9 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -209,6 +209,88 @@ static int xive2_router_get_block_id(Xive2Router *xrtr) > return xrc->get_block_id(xrtr); > } > > +/* > + * Encode the HW CAM line with 7bit or 8bit thread id. The thread id > + * width and block id width is configurable at the IC level. > + * > + * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) > + * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) > + */ > +static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) > +{ > + Xive2Router *xrtr = XIVE2_ROUTER(xptr); > + CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; > + uint32_t pir = env->spr_cb[SPR_PIR].default_value; > + uint8_t blk = xive2_router_get_block_id(xrtr); > + uint8_t tid_shift = 7; > + uint8_t tid_mask = (1 << tid_shift) - 1; > + > + return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); > +} > + > +/* > + * The thread context register words are in big-endian format. > + */ > +int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, > + uint8_t format, > + uint8_t nvt_blk, uint32_t nvt_idx, > + bool cam_ignore, uint32_t logic_serv) > +{ > + uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); > + uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); > + uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); > + uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); > + uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); > + > + /* > + * TODO (PowerNV): ignore mode. The low order bits of the NVT > + * identifier are ignored in the "CAM" match. > + */ > + > + if (format == 0) { > + if (cam_ignore == true) { > + /* > + * F=0 & i=1: Logical server notification (bits ignored at > + * the end of the NVT identifier) > + */ > + qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", > + nvt_blk, nvt_idx); > + return -1; > + } > + > + /* F=0 & i=0: Specific NVT notification */ > + > + /* PHYS ring */ > + if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && > + cam == xive2_tctx_hw_cam_line(xptr, tctx)) { > + return TM_QW3_HV_PHYS; > + } > + > + /* HV POOL ring */ > + if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && > + cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) { > + return TM_QW2_HV_POOL; > + } > + > + /* OS ring */ > + if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && > + cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) { > + return TM_QW1_OS; > + } > + } else { > + /* F=1 : User level Event-Based Branch (EBB) notification */ > + > + /* USER ring */ > + if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && > + (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && > + (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && > + (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { > + return TM_QW0_USER; > + } > + } > + return -1; > +} > + > static void xive2_router_realize(DeviceState *dev, Error **errp) > { > Xive2Router *xrtr = XIVE2_ROUTER(dev);