From: Richard Henderson <richard.henderson@linaro.org>
To: lixianglai <lixianglai@loongson.cn>, qemu-devel@nongnu.org
Cc: maobibo@loongson.cn, Song Gao <gaosong@loongson.cn>,
Xiaojuan Yang <yangxiaojuan@loongson.cn>,
zhaotianrui@loongson.cn
Subject: Re: [PATCH V2 1/1] target/loongarch: Fixed tlb huge page loading issue
Date: Tue, 5 Mar 2024 18:10:07 -1000 [thread overview]
Message-ID: <fa6b408c-43fd-4011-b704-ac7ae256fcbf@linaro.org> (raw)
In-Reply-To: <5325b63b-2a51-8448-bf70-c0659497db61@loongson.cn>
On 3/5/24 17:52, lixianglai wrote:
> The LDDIR_PS variable is not described in detail in the manual, but is only an
> intermediate variable to assist in page size calculation during tcg simulation.
This is exactly why I believe adding this intermediate variable is wrong.
What happens if LDPTE is *not* preceded by LDDIR? It's not the usual way a tlb fill
routine works, but *something* should happen if you construct a valid huge page tlb entry
by hand and pass it directly to LDPTE.
With your implementation, this will not work because lddir_ps will not be initialized.
But I expect that on real hardware it would work.
If this does not work on real hardware, then there *is* some heretofore undocumented
hardware state. If so, then we need a description of this state from the hardware
engineers -- the documentation of LDDIR and LDPTE need updating. Finally, this new
hardware state needs to be added to the migration state.
r~
next prev parent reply other threads:[~2024-03-06 4:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-05 3:51 [PATCH V2 0/1] target/loongarch: Fixed tlb huge page loading issue Xianglai Li
2024-03-05 3:51 ` [PATCH V2 1/1] " Xianglai Li
2024-03-05 4:34 ` Richard Henderson
2024-03-05 6:21 ` lixianglai
2024-03-05 15:37 ` Richard Henderson
2024-03-06 3:52 ` lixianglai
2024-03-06 4:10 ` Richard Henderson [this message]
2024-03-06 7:38 ` maobibo
2024-03-06 17:46 ` Richard Henderson
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