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Tue, 05 Mar 2024 01:19:17 -0800 (PST) Message-ID: Date: Tue, 5 Mar 2024 10:19:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: Fix 32-bit SMOPA Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-stable@nongnu.org References: <20240305023116.234256-1-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240305023116.234256-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 5/3/24 03:31, Richard Henderson wrote: > The while the 8-bit input elements are sequential in the input vector, > the 32-bit output elements are not sequential in the output matrix. > Do not attempt to compute 2 32-bit outputs at the same time. > > Cc: qemu-stable@nongnu.org > Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product") > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083 > Signed-off-by: Richard Henderson > --- > target/arm/tcg/sme_helper.c | 77 ++++++++++++++++++------------- > tests/tcg/aarch64/sme-smopa-1.c | 47 +++++++++++++++++++ > tests/tcg/aarch64/sme-smopa-2.c | 54 ++++++++++++++++++++++ > tests/tcg/aarch64/Makefile.target | 2 +- > 4 files changed, 147 insertions(+), 33 deletions(-) > create mode 100644 tests/tcg/aarch64/sme-smopa-1.c > create mode 100644 tests/tcg/aarch64/sme-smopa-2.c > > diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c > index 904bfdac43..ef39eee48d 100644 > --- a/target/arm/tcg/sme_helper.c > +++ b/target/arm/tcg/sme_helper.c > @@ -1083,11 +1083,32 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, > } > } > > -typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); > +typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool); > +static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm, > + uint8_t *pn, uint8_t *pm, > + uint32_t desc, IMOPFn32 *fn) > +{ > + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; > + bool neg = simd_data(desc); > > -static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, > - uint8_t *pn, uint8_t *pm, > - uint32_t desc, IMOPFn *fn) > + for (row = 0; row < oprsz; ++row) { > + uint8_t pa = pn[H1(row >> 1)] >> ((row & 1) * 4); > + uint32_t *za_row = &za[H4(tile_vslice_index(row))]; > + uint32_t n = zn[H4(row)]; > + > + for (col = 0; col < oprsz; ++col) { > + uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4); > + uint32_t *a = &za_row[col]; Shouldn't this be: uint32_t *a = &za_row[H4(col)]; to work on big endian hosts? > + > + *a = fn(n, zm[H4(col)], *a, pa & pb & 0xf, neg); > + } > + } > +} > + > +typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool); > +static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm, > + uint8_t *pn, uint8_t *pm, > + uint32_t desc, IMOPFn64 *fn) > { > intptr_t row, col, oprsz = simd_oprsz(desc) / 8; > bool neg = simd_data(desc); > @@ -1107,25 +1128,16 @@ static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, > } > > #define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ > -static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ > +static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \ > { \ > - uint32_t sum0 = 0, sum1 = 0; \ > + uint32_t sum = 0; \ > /* Apply P to N as a mask, making the inactive elements 0. */ \ > n &= expand_pred_b(p); \ > - sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ > - sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ > - sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ > - sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ > - sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ > - sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \ > - sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ > - sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \ > - if (neg) { \ > - sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \ > - } else { \ > - sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \ > - } \ > - return ((uint64_t)sum1 << 32) | sum0; \ > + sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ > + sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ > + sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ > + sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ > + return neg ? a - sum : a + sum; \ > }