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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id v8sm6354241pjf.46.2020.07.10.11.06.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jul 2020 11:06:59 -0700 (PDT) Subject: Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20200710104920.13550-1-frank.chang@sifive.com> <20200710104920.13550-14-frank.chang@sifive.com> From: Richard Henderson Message-ID: Date: Fri, 10 Jul 2020 11:06:57 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200710104920.13550-14-frank.chang@sifive.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , LIU Zhiwei , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/10/20 3:48 AM, frank.chang@sifive.com wrote: > -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) > +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a) Do not mix this change with anything else. > + rd = tcg_const_i32(a->rd); > + rs1 = tcg_const_i32(a->rs1); Any time you put a register number into a tcg const, there's probably a better way to do things. > - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ > - if (a->rs1 == 0) { > - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ > - s1 = tcg_const_tl(RV_VLEN_MAX); > - } else { > - s1 = tcg_temp_new(); > - gen_get_gpr(s1, a->rs1); > - } E.g. this code should be kept, and add if (a->rd == 0 && a->rs1 == 0) { s1 = tcg_temp_new(); tcg_gen_mov_tl(s1, cpu_vl); } else ... > + if ((sew > cpu->cfg.elen) > + || vill > + || vflmul < ((float)sew / cpu->cfg.elen) > + || (ediv != 0) > + || (reserved != 0)) { > /* only set vill bit. */ > env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); > - env->vl = 0; > - env->vstart = 0; > return 0; > } You do need to check 0.7.1 so long as it's supported. r~