* [Qemu-devel] [PATCH] TC6393xb update: support system features
@ 2008-06-05 18:11 Dmitry Baryshkov
2008-06-08 7:20 ` [Qemu-devel] " Dmitry Baryshkov
0 siblings, 1 reply; 4+ messages in thread
From: Dmitry Baryshkov @ 2008-06-05 18:11 UTC (permalink / raw)
To: qemu-devel
Add basic support for TC6393XB system features. No support for GPIO
input though.
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
---
Makefile.target | 2 +-
hw/devices.h | 8 ++
hw/tc6393xb.c | 290 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/tosa.c | 38 +-------
4 files changed, 301 insertions(+), 37 deletions(-)
create mode 100644 hw/tc6393xb.c
diff --git a/Makefile.target b/Makefile.target
index e06a99e..e1cd403 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -585,7 +585,7 @@ OBJS+= arm-semi.o
OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
OBJS+= pflash_cfi01.o gumstix.o
-OBJS+= zaurus.o ide.o serial.o nand.o ecc.o spitz.o tosa.o
+OBJS+= zaurus.o ide.o serial.o nand.o ecc.o spitz.o tosa.o tc6393xb.o
OBJS+= omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
OBJS+= omap2.o omap_dss.o
OBJS+= palm.o tsc210x.o
diff --git a/hw/devices.h b/hw/devices.h
index 948abc5..7b26f3e 100644
--- a/hw/devices.h
+++ b/hw/devices.h
@@ -64,4 +64,12 @@ int tusb6010_sync_io(struct tusb_s *s);
int tusb6010_async_io(struct tusb_s *s);
void tusb6010_power(struct tusb_s *s, int on);
+/* tc6393xb.c */
+struct tc6393xb_s;
+struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq);
+void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
+ qemu_irq handler);
+qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s);
+
+
#endif
diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
new file mode 100644
index 0000000..3a6d531
--- /dev/null
+++ b/hw/tc6393xb.c
@@ -0,0 +1,290 @@
+/* vim:set shiftwidth=4 ts=4 et: */
+#include "hw.h"
+#include "pxa.h"
+#include "devices.h"
+
+#define TC6393XB_GPIOS 16
+
+#define SCR_REVID 0x08 /* b Revision ID */
+#define SCR_ISR 0x50 /* b Interrupt Status */
+#define SCR_IMR 0x52 /* b Interrupt Mask */
+#define SCR_IRR 0x54 /* b Interrupt Routing */
+#define SCR_GPER 0x60 /* w GP Enable */
+#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
+#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
+#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
+#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
+#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
+#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
+#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
+#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
+#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
+#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
+#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
+#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
+#define SCR_CCR 0x98 /* w Clock Control */
+#define SCR_PLL2CR 0x9a /* w PLL2 Control */
+#define SCR_PLL1CR 0x9c /* l PLL1 Control */
+#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
+#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
+#define SCR_FER 0xe0 /* b Function Enable */
+#define SCR_MCR 0xe4 /* w Mode Control */
+#define SCR_CONFIG 0xfc /* b Configuration Control */
+#define SCR_DEBUG 0xff /* b Debug */
+
+struct tc6393xb_s {
+ target_phys_addr_t target_base;
+ struct {
+ uint8_t ISR;
+ uint8_t IMR;
+ uint8_t IRR;
+ uint16_t GPER;
+ uint8_t GPI_SR[3];
+ uint8_t GPI_IMR[3];
+ uint8_t GPI_EDER[3];
+ uint8_t GPI_LIR[3];
+ uint8_t GP_IARCR[3];
+ uint8_t GP_IARLCR[3];
+ uint8_t GPI_BCR[3];
+ uint16_t GPA_IARCR;
+ uint16_t GPA_IARLCR;
+ uint16_t CCR;
+ uint16_t PLL2CR;
+ uint32_t PLL1CR;
+ uint8_t DIARCR;
+ uint8_t DBOCR;
+ uint8_t FER;
+ uint16_t MCR;
+ uint8_t CONFIG;
+ uint8_t DEBUG;
+ } scr;
+ uint32_t gpio_dir;
+ uint32_t gpio_level;
+ uint32_t prev_level;
+ qemu_irq handler[TC6393XB_GPIOS];
+ qemu_irq *gpio_in;
+};
+
+qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s)
+{
+ return s->gpio_in;
+}
+
+static void tc6393xb_gpio_set(void *opaque, int line, int level)
+{
+// struct tc6393xb_s *s = opaque;
+
+ if (line > TC6393XB_GPIOS) {
+ printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
+ return;
+ }
+
+ // FIXME: how does the chip reflect the GPIO input level change?
+}
+
+void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
+ qemu_irq handler)
+{
+ if (line >= TC6393XB_GPIOS) {
+ fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
+ return;
+ }
+
+ s->handler[line] = handler;
+}
+
+static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s)
+{
+ uint32_t level, diff;
+ int bit;
+
+ level = s->gpio_level & s->gpio_dir;
+
+ for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
+ bit = ffs(diff) - 1;
+ qemu_set_irq(s->handler[bit], (level >> bit) & 1);
+ }
+
+ s->prev_level = level;
+}
+
+#define SCR_REG_B(N) \
+ case SCR_ ##N: return s->scr.N
+#define SCR_REG_W(N) \
+ case SCR_ ##N: return s->scr.N; \
+ case SCR_ ##N + 1: return s->scr.N >> 8;
+#define SCR_REG_L(N) \
+ case SCR_ ##N: return s->scr.N; \
+ case SCR_ ##N + 1: return s->scr.N >> 8; \
+ case SCR_ ##N + 2: return s->scr.N >> 16; \
+ case SCR_ ##N + 3: return s->scr.N >> 24;
+#define SCR_REG_A(N) \
+ case SCR_ ##N(0): return s->scr.N[0]; \
+ case SCR_ ##N(1): return s->scr.N[1]; \
+ case SCR_ ##N(2): return s->scr.N[2]
+
+static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr)
+{
+ struct tc6393xb_s *s = opaque;
+ addr -= s->target_base;
+ switch (addr) {
+ case SCR_REVID:
+ return 3;
+ case SCR_REVID+1:
+ return 0;
+ SCR_REG_B(ISR);
+ SCR_REG_B(IMR);
+ SCR_REG_B(IRR);
+ SCR_REG_W(GPER);
+ SCR_REG_A(GPI_SR);
+ SCR_REG_A(GPI_IMR);
+ SCR_REG_A(GPI_EDER);
+ SCR_REG_A(GPI_LIR);
+ case SCR_GPO_DSR(0):
+ case SCR_GPO_DSR(1):
+ case SCR_GPO_DSR(2):
+ return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
+ case SCR_GPO_DOECR(0):
+ case SCR_GPO_DOECR(1):
+ case SCR_GPO_DOECR(2):
+ return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
+ SCR_REG_A(GP_IARCR);
+ SCR_REG_A(GP_IARLCR);
+ SCR_REG_A(GPI_BCR);
+ SCR_REG_W(GPA_IARCR);
+ SCR_REG_W(GPA_IARLCR);
+ SCR_REG_W(CCR);
+ SCR_REG_W(PLL2CR);
+ SCR_REG_L(PLL1CR);
+ SCR_REG_B(DIARCR);
+ SCR_REG_B(DBOCR);
+ SCR_REG_B(FER);
+ SCR_REG_W(MCR);
+ SCR_REG_B(CONFIG);
+ SCR_REG_B(DEBUG);
+ }
+ fprintf(stderr, "tc6393xb: unhandled read at %08x\n", addr);
+ return 0;
+}
+#undef SCR_REG_B
+#undef SCR_REG_W
+#undef SCR_REG_L
+#undef SCR_REG_A
+
+#define SCR_REG_B(N) \
+ case SCR_ ##N: s->scr.N = value; break;
+#define SCR_REG_W(N) \
+ case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); break; \
+ case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); break
+#define SCR_REG_L(N) \
+ case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); break; \
+ case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); break; \
+ case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); break; \
+ case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); break;
+#define SCR_REG_A(N) \
+ case SCR_ ##N(0): s->scr.N[0] = value; break; \
+ case SCR_ ##N(1): s->scr.N[1] = value; break; \
+ case SCR_ ##N(2): s->scr.N[2] = value; break
+
+static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+ struct tc6393xb_s *s = opaque;
+ addr -= s->target_base;
+ switch (addr) {
+ SCR_REG_B(ISR);
+ SCR_REG_B(IMR);
+ SCR_REG_B(IRR);
+ SCR_REG_W(GPER);
+ SCR_REG_A(GPI_SR);
+ SCR_REG_A(GPI_IMR);
+ SCR_REG_A(GPI_EDER);
+ SCR_REG_A(GPI_LIR);
+ case SCR_GPO_DSR(0):
+ case SCR_GPO_DSR(1):
+ case SCR_GPO_DSR(2):
+ s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
+ tc6393xb_gpio_handler_update(s);
+ break;
+ case SCR_GPO_DOECR(0):
+ case SCR_GPO_DOECR(1):
+ case SCR_GPO_DOECR(2):
+ s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
+ tc6393xb_gpio_handler_update(s);
+ break;
+ SCR_REG_A(GP_IARCR);
+ SCR_REG_A(GP_IARLCR);
+ SCR_REG_A(GPI_BCR);
+ SCR_REG_W(GPA_IARCR);
+ SCR_REG_W(GPA_IARLCR);
+ SCR_REG_W(CCR);
+ SCR_REG_W(PLL2CR);
+ SCR_REG_L(PLL1CR);
+ SCR_REG_B(DIARCR);
+ SCR_REG_B(DBOCR);
+ SCR_REG_B(FER);
+ SCR_REG_W(MCR);
+ SCR_REG_B(CONFIG);
+ SCR_REG_B(DEBUG);
+ default:
+ fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n", addr, value & 0xff);
+ break;
+ }
+}
+#undef SCR_REG_B
+#undef SCR_REG_W
+#undef SCR_REG_L
+#undef SCR_REG_A
+
+static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr)
+{
+ return (tc6393xb_readb(opaque, addr) & 0xff) |
+ (tc6393xb_readb(opaque, addr + 1) << 8);
+}
+
+static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr)
+{
+ return (tc6393xb_readb(opaque, addr) & 0xff) |
+ ((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) |
+ ((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) |
+ ((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24);
+}
+
+static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+ tc6393xb_writeb(opaque, addr, value);
+ tc6393xb_writeb(opaque, addr + 1, value >> 8);
+}
+
+static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+ tc6393xb_writeb(opaque, addr, value);
+ tc6393xb_writeb(opaque, addr + 1, value >> 8);
+ tc6393xb_writeb(opaque, addr + 2, value >> 16);
+ tc6393xb_writeb(opaque, addr + 3, value >> 24);
+}
+
+struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq)
+{
+ int iomemtype;
+ struct tc6393xb_s *s;
+ CPUReadMemoryFunc *tc6393xb_readfn[] = {
+ tc6393xb_readb,
+ tc6393xb_readw,
+ tc6393xb_readl,
+ };
+ CPUWriteMemoryFunc *tc6393xb_writefn[] = {
+ tc6393xb_writeb,
+ tc6393xb_writew,
+ tc6393xb_writel,
+ };
+
+ s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s));
+ s->target_base = base;
+ s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
+
+ iomemtype = cpu_register_io_memory(0, tc6393xb_readfn,
+ tc6393xb_writefn, s);
+ cpu_register_physical_memory(s->target_base, 0x200000, iomemtype);
+
+ return s;
+}
diff --git a/hw/tosa.c b/hw/tosa.c
index 97d41ec..f67d67e 100644
--- a/hw/tosa.c
+++ b/hw/tosa.c
@@ -12,6 +12,7 @@
#include "pxa.h"
#include "arm-misc.h"
#include "sysemu.h"
+#include "devices.h"
#include "sharpsl.h"
#include "pcmcia.h"
#include "block.h"
@@ -31,41 +32,6 @@
#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
-struct tc6393xb_s {
- target_phys_addr_t target_base;
-};
-
-static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr)
-{
- return 3;
-}
-static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
-}
-static void tosa_tc6393xb_register(struct pxa2xx_state_s *cpu)
-{
- int iomemtype;
- struct tc6393xb_s *s;
- CPUReadMemoryFunc *tc6393xb_readfn[] = {
- tc6393xb_readb,
- tc6393xb_readb,
- tc6393xb_readb,
- };
- CPUWriteMemoryFunc *tc6393xb_writefn[] = {
- tc6393xb_writeb,
- tc6393xb_writeb,
- tc6393xb_writeb,
- };
-
- s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s));
- s->target_base = 0x10000000;
-
- iomemtype = cpu_register_io_memory(0, tc6393xb_readfn,
- tc6393xb_writefn, s);
- cpu_register_physical_memory(s->target_base, 0x200000, iomemtype);
-}
-
static void tosa_microdrive_attach(struct pxa2xx_state_s *cpu)
{
struct pcmcia_card_s *md;
@@ -132,7 +98,7 @@ static void tosa_init(ram_addr_t ram_size, int vga_ram_size,
cpu_register_physical_memory(0, TOSA_ROM,
qemu_ram_alloc(TOSA_ROM) | IO_MEM_ROM);
- tosa_tc6393xb_register(cpu);
+ tc6393xb_init(0x10000000, NULL);
scp0 = scoop_init(cpu, 0, 0x08800000);
scp1 = scoop_init(cpu, 1, 0x14800040);
--
1.5.5.1
--
With best wishes
Dmitry
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Qemu-devel] Re: [PATCH] TC6393xb update: support system features
2008-06-05 18:11 [Qemu-devel] [PATCH] TC6393xb update: support system features Dmitry Baryshkov
@ 2008-06-08 7:20 ` Dmitry Baryshkov
2008-06-08 23:06 ` andrzej zaborowski
0 siblings, 1 reply; 4+ messages in thread
From: Dmitry Baryshkov @ 2008-06-08 7:20 UTC (permalink / raw)
To: qemu-devel; +Cc: balrog
Hi,
On Thu, Jun 05, 2008 at 10:11:56PM +0400, Dmitry Baryshkov wrote:
> Add basic support for TC6393XB system features. No support for GPIO
> input though.
>
> Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
> ---
> Makefile.target | 2 +-
> hw/devices.h | 8 ++
> hw/tc6393xb.c | 290 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/tosa.c | 38 +-------
> 4 files changed, 301 insertions(+), 37 deletions(-)
> create mode 100644 hw/tc6393xb.c
Any comments about this? TC6393xb is a multifunctional device as found
in tosa or some toshibe e-series PDAs. And this provides some partial
emulation of it's features.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] Re: [PATCH] TC6393xb update: support system features
2008-06-08 7:20 ` [Qemu-devel] " Dmitry Baryshkov
@ 2008-06-08 23:06 ` andrzej zaborowski
2008-06-08 23:21 ` Paul Brook
0 siblings, 1 reply; 4+ messages in thread
From: andrzej zaborowski @ 2008-06-08 23:06 UTC (permalink / raw)
To: qemu-devel
Hi,
On 08/06/2008, Dmitry Baryshkov <dbaryshkov@gmail.com> wrote:
> Any comments about this? TC6393xb is a multifunctional device as found
> in tosa or some toshibe e-series PDAs. And this provides some partial
> emulation of it's features.
Committed, thanks. Perhaps it's good to have at least a short license
notice and a note on what the device does or who produces it. I think
it's not a policy though.
Cheers
--
Please do not print this email unless absolutely necessary. Spread
environmental awareness.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] Re: [PATCH] TC6393xb update: support system features
2008-06-08 23:06 ` andrzej zaborowski
@ 2008-06-08 23:21 ` Paul Brook
0 siblings, 0 replies; 4+ messages in thread
From: Paul Brook @ 2008-06-08 23:21 UTC (permalink / raw)
To: qemu-devel
On Monday 09 June 2008, andrzej zaborowski wrote:
> Hi,
>
> On 08/06/2008, Dmitry Baryshkov <dbaryshkov@gmail.com> wrote:
> > Any comments about this? TC6393xb is a multifunctional device as found
> > in tosa or some toshibe e-series PDAs. And this provides some partial
> > emulation of it's features.
>
> Committed, thanks. Perhaps it's good to have at least a short license
> notice
Licence notes and at least basic copyright information should definitely be
required.
> and a note on what the device does or who produces it. I think
> it's not a policy though.
I'd also strongly recommend that these be added. I find it very useful to
have a short comment saying exactly what device we're trying to emulate.
> +/* vim:set shiftwidth=4 ts=4 et: */
We can loose this though.
Paul
^ permalink raw reply [flat|nested] 4+ messages in thread
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2008-06-05 18:11 [Qemu-devel] [PATCH] TC6393xb update: support system features Dmitry Baryshkov
2008-06-08 7:20 ` [Qemu-devel] " Dmitry Baryshkov
2008-06-08 23:06 ` andrzej zaborowski
2008-06-08 23:21 ` Paul Brook
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