[Qemu-devel] [PATCH] SH: r2d pci support.

[Qemu-devel] [PATCH] SH: r2d pci support.

[takasi-y]

This patch adds pci support to sh/r2d board.
This is the first user of PCIC support I formerly sent.

PCIC actually is inside of chip with CPU core on SH7751.
But, this code is written as if SH7750 and PCIC are on board.
I care little about physical device boundary, but fitting with qemu's design.

This patch also adds some BSC(Bus State Controller) registers,
because PCI device driver software have to accesses them.

/yoshii

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
---
 hw/r2d.c    |   26 ++++++++++++++++++++++++++
 hw/sh7750.c |   17 +++++++++++++++++
 2 files changed, 43 insertions(+), 0 deletions(-)

diff --git a/hw/r2d.c b/hw/r2d.c
index f818711..54529ca 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -27,6 +27,9 @@
 #include "sh.h"
 #include "sysemu.h"
 #include "boards.h"
+#include "pci.h"
+#include "net.h"
+#include "sh7750_regs.h"
 
 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
 #define SDRAM_SIZE 0x04000000
@@ -183,6 +186,17 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 }
 
+static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
+{
+    qemu_set_irq(p[n], l);
+}
+
+static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
+{
+    const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
+    return intx[d->devfn>>3];
+}
+
 static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
               const char *boot_device, DisplayState * ds,
 	      const char *kernel_filename, const char *kernel_cmdline,
@@ -191,6 +205,8 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
     CPUState *env;
     struct SH7750State *s;
     qemu_irq *irq;
+    PCIBus *pci;
+    int i;
 
     if (!cpu_model)
         cpu_model = "SH7751R";
@@ -206,14 +222,24 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
     /* Register peripherals */
     s = sh7750_init(env);
     irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
+    pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
 
     /* onboard CF (True IDE mode, Master only). */
     mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
         drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL);
+    /* NIC: rtl8139 on-board, and 2 slots. */
+    pci_rtl8139_init(pci, &nd_table[0], 2<<3);
+    for (i = 1; i < nb_nics; i++)
+        pci_nic_init(pci, &nd_table[i], -1);
 
     /* Todo: register on board registers */
     {
       int kernel_size;
+      /* initialization which should be done by firmware */
+      uint32_t bcr1 = 1<<3; // cs3 SDRAM
+      uint16_t bcr2 = 3<<(3*2); // cs3 32bit
+      cpu_physical_memory_write(SH7750_BCR1_A7,&bcr1,4);
+      cpu_physical_memory_write(SH7750_BCR2_A7,&bcr2,2);
 
       kernel_size = load_image(kernel_filename, phys_ram_base);
 
diff --git a/hw/sh7750.c b/hw/sh7750.c
index ace3b83..4ae90b1 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -41,6 +41,8 @@ typedef struct SH7750State {
     /* Peripheral frequency in Hz */
     uint32_t periph_freq;
     /* SDRAM controller */
+    uint32_t bcr1;
+    uint32_t bcr2;
     uint16_t rfcr;
     /* IO ports */
     uint16_t gpioic;
@@ -208,6 +210,8 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
     SH7750State *s = opaque;
 
     switch (addr) {
+    case SH7750_BCR2_A7:
+	return s->bcr2;
     case SH7750_FRQCR_A7:
 	return 0;
     case SH7750_RFCR_A7:
@@ -231,6 +235,15 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
     SH7750State *s = opaque;
 
     switch (addr) {
+    case SH7750_BCR1_A7:
+	return s->bcr1;
+    case SH7750_BCR4_A7:
+    case SH7750_WCR1_A7:
+    case SH7750_WCR2_A7:
+    case SH7750_WCR3_A7:
+    case SH7750_MCR_A7:
+	ignore_access("long read", addr);
+	return 0;
     case SH7750_MMUCR_A7:
 	return s->cpu->mmucr;
     case SH7750_PTEH_A7:
@@ -285,6 +298,8 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
     switch (addr) {
 	/* SDRAM controller */
     case SH7750_BCR2_A7:
+	s->bcr2 = mem_value;
+	return;
     case SH7750_BCR3_A7:
     case SH7750_RTCOR_A7:
     case SH7750_RTCNT_A7:
@@ -331,6 +346,8 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
     switch (addr) {
 	/* SDRAM controller */
     case SH7750_BCR1_A7:
+	s->bcr1 = mem_value;
+        return;
     case SH7750_BCR4_A7:
     case SH7750_WCR1_A7:
     case SH7750_WCR2_A7:
-- 
1.5.6.3

Re: [Qemu-devel] [PATCH] SH: r2d pci support.

[andrzej zaborowski]

Hi,

2008/11/3  <takasi-y@ops.dti.ne.jp>:
> This patch adds pci support to sh/r2d board.
> This is the first user of PCIC support I formerly sent.
>
> PCIC actually is inside of chip with CPU core on SH7751.
> But, this code is written as if SH7750 and PCIC are on board.
> I care little about physical device boundary, but fitting with qemu's design.
>
> This patch also adds some BSC(Bus State Controller) registers,
> because PCI device driver software have to accesses them.
>
> /yoshii
>
> Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
> ---
>  hw/r2d.c    |   26 ++++++++++++++++++++++++++
>  hw/sh7750.c |   17 +++++++++++++++++
>  2 files changed, 43 insertions(+), 0 deletions(-)
>
> diff --git a/hw/r2d.c b/hw/r2d.c
> index f818711..54529ca 100644
> --- a/hw/r2d.c
> +++ b/hw/r2d.c
> @@ -27,6 +27,9 @@
>  #include "sh.h"
>  #include "sysemu.h"
>  #include "boards.h"
> +#include "pci.h"
> +#include "net.h"
> +#include "sh7750_regs.h"
>
>  #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
>  #define SDRAM_SIZE 0x04000000
> @@ -183,6 +186,17 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
>     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
>  }
>
> +static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
> +{
> +    qemu_set_irq(p[n], l);
> +}
> +
> +static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
> +{
> +    const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
> +    return intx[d->devfn>>3];
> +}
> +
>  static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
>               const char *boot_device, DisplayState * ds,
>              const char *kernel_filename, const char *kernel_cmdline,
> @@ -191,6 +205,8 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
>     CPUState *env;
>     struct SH7750State *s;
>     qemu_irq *irq;
> +    PCIBus *pci;
> +    int i;
>
>     if (!cpu_model)
>         cpu_model = "SH7751R";
> @@ -206,14 +222,24 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
>     /* Register peripherals */
>     s = sh7750_init(env);
>     irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
> +    pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
>
>     /* onboard CF (True IDE mode, Master only). */
>     mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
>         drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL);
> +    /* NIC: rtl8139 on-board, and 2 slots. */
> +    pci_rtl8139_init(pci, &nd_table[0], 2<<3);
> +    for (i = 1; i < nb_nics; i++)
> +        pci_nic_init(pci, &nd_table[i], -1);
>
>     /* Todo: register on board registers */
>     {
>       int kernel_size;
> +      /* initialization which should be done by firmware */
> +      uint32_t bcr1 = 1<<3; // cs3 SDRAM
> +      uint16_t bcr2 = 3<<(3*2); // cs3 32bit
> +      cpu_physical_memory_write(SH7750_BCR1_A7,&bcr1,4);
> +      cpu_physical_memory_write(SH7750_BCR2_A7,&bcr2,2);

I pushed this patch but it looks like there may be an endianness problem here.

Cheers

[Qemu-devel] [PATCH] sh4: r2d. Endian conversion for peripheral register initialization.

[takasi-y]

Add endian conversion to hw/r2d.c which lacks consideration of endian on
setting BSC registers.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
---

Ah, thank you for pointed it out.
> > +      cpu_physical_memory_write(SH7750_BCR1_A7,&bcr1,4);
> > +      cpu_physical_memory_write(SH7750_BCR2_A7,&bcr2,2);
> 
> I pushed this patch but it looks like there may be an endianness problem here.
I found what I wanted might be stl_phys/stw_phys.

This time I set up big endian target system, and tested both endian.
But, I still in trouble setting up big endian host.
Because I don't have real HW here, I tried qemu sparc, mipsel and ppc,
 but none of them are successful, so far.
Could someone tell me which arch is recommended for testing host ?

Cheers,
/yoshii

---
 hw/r2d.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/r2d.c b/hw/r2d.c
index 5d5eb1e..b3aa6e9 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -238,10 +238,8 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
     {
       int kernel_size;
       /* initialization which should be done by firmware */
-      uint32_t bcr1 = 1 << 3; /* cs3 SDRAM */
-      uint16_t bcr2 = 3 << (3 * 2); /* cs3 32-bit */
-      cpu_physical_memory_write(SH7750_BCR1_A7, (uint8_t *)&bcr1, 4);
-      cpu_physical_memory_write(SH7750_BCR2_A7, (uint8_t *)&bcr2, 2);
+      stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
+      stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
 
       kernel_size = load_image(kernel_filename, phys_ram_base);
 
-- 
1.5.6.3

Re: [Qemu-devel] [PATCH] sh4: r2d. Endian conversion for peripheral register initialization.

[Aurelien Jarno]

On Mon, Dec 15, 2008 at 02:52:24AM +0900, takasi-y@ops.dti.ne.jp wrote:
> Add endian conversion to hw/r2d.c which lacks consideration of endian on
> setting BSC registers.
> 
> Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
> ---

Thanks, applied.

> Ah, thank you for pointed it out.
> > > +      cpu_physical_memory_write(SH7750_BCR1_A7,&bcr1,4);
> > > +      cpu_physical_memory_write(SH7750_BCR2_A7,&bcr2,2);
> > 
> > I pushed this patch but it looks like there may be an endianness problem here.
> I found what I wanted might be stl_phys/stw_phys.
> 
> This time I set up big endian target system, and tested both endian.
> But, I still in trouble setting up big endian host.
> Because I don't have real HW here, I tried qemu sparc, mipsel and ppc,
>  but none of them are successful, so far.
> Could someone tell me which arch is recommended for testing host ?
> 
> Cheers,
> /yoshii
> 
> ---
>  hw/r2d.c |    6 ++----
>  1 files changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/r2d.c b/hw/r2d.c
> index 5d5eb1e..b3aa6e9 100644
> --- a/hw/r2d.c
> +++ b/hw/r2d.c
> @@ -238,10 +238,8 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
>      {
>        int kernel_size;
>        /* initialization which should be done by firmware */
> -      uint32_t bcr1 = 1 << 3; /* cs3 SDRAM */
> -      uint16_t bcr2 = 3 << (3 * 2); /* cs3 32-bit */
> -      cpu_physical_memory_write(SH7750_BCR1_A7, (uint8_t *)&bcr1, 4);
> -      cpu_physical_memory_write(SH7750_BCR2_A7, (uint8_t *)&bcr2, 2);
> +      stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
> +      stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
>  
>        kernel_size = load_image(kernel_filename, phys_ram_base);
>  
> -- 
> 1.5.6.3
> 
> 
> 
> 

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net