From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L9PCE-00025O-Q8 for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:21:38 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L9PCC-00023J-8h for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:21:37 -0500 Received: from [199.232.76.173] (port=55022 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L9PCB-00022x-9j for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:21:35 -0500 Received: from rv-out-0708.google.com ([209.85.198.245]:29945) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L9PCA-0001JI-Oq for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:21:35 -0500 Received: by rv-out-0708.google.com with SMTP id f25so811550rvb.22 for ; Sun, 07 Dec 2008 11:21:33 -0800 (PST) Message-ID: Date: Sun, 7 Dec 2008 20:21:33 +0100 From: "andrzej zaborowski" Subject: Re: [Qemu-devel] [PATCH] SH: r2d pci support. In-Reply-To: <200811031623.mA3GNT12001126@smtp12.dti.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <200811031623.mA3GNT12001126@smtp12.dti.ne.jp> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi, 2008/11/3 : > This patch adds pci support to sh/r2d board. > This is the first user of PCIC support I formerly sent. > > PCIC actually is inside of chip with CPU core on SH7751. > But, this code is written as if SH7750 and PCIC are on board. > I care little about physical device boundary, but fitting with qemu's design. > > This patch also adds some BSC(Bus State Controller) registers, > because PCI device driver software have to accesses them. > > /yoshii > > Signed-off-by: Takashi YOSHII > --- > hw/r2d.c | 26 ++++++++++++++++++++++++++ > hw/sh7750.c | 17 +++++++++++++++++ > 2 files changed, 43 insertions(+), 0 deletions(-) > > diff --git a/hw/r2d.c b/hw/r2d.c > index f818711..54529ca 100644 > --- a/hw/r2d.c > +++ b/hw/r2d.c > @@ -27,6 +27,9 @@ > #include "sh.h" > #include "sysemu.h" > #include "boards.h" > +#include "pci.h" > +#include "net.h" > +#include "sh7750_regs.h" > > #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ > #define SDRAM_SIZE 0x04000000 > @@ -183,6 +186,17 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl) > return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); > } > > +static void r2d_pci_set_irq(qemu_irq *p, int n, int l) > +{ > + qemu_set_irq(p[n], l); > +} > + > +static int r2d_pci_map_irq(PCIDevice *d, int irq_num) > +{ > + const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD }; > + return intx[d->devfn>>3]; > +} > + > static void r2d_init(ram_addr_t ram_size, int vga_ram_size, > const char *boot_device, DisplayState * ds, > const char *kernel_filename, const char *kernel_cmdline, > @@ -191,6 +205,8 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size, > CPUState *env; > struct SH7750State *s; > qemu_irq *irq; > + PCIBus *pci; > + int i; > > if (!cpu_model) > cpu_model = "SH7751R"; > @@ -206,14 +222,24 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size, > /* Register peripherals */ > s = sh7750_init(env); > irq = r2d_fpga_init(0x04000000, sh7750_irl(s)); > + pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4); > > /* onboard CF (True IDE mode, Master only). */ > mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1, > drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL); > + /* NIC: rtl8139 on-board, and 2 slots. */ > + pci_rtl8139_init(pci, &nd_table[0], 2<<3); > + for (i = 1; i < nb_nics; i++) > + pci_nic_init(pci, &nd_table[i], -1); > > /* Todo: register on board registers */ > { > int kernel_size; > + /* initialization which should be done by firmware */ > + uint32_t bcr1 = 1<<3; // cs3 SDRAM > + uint16_t bcr2 = 3<<(3*2); // cs3 32bit > + cpu_physical_memory_write(SH7750_BCR1_A7,&bcr1,4); > + cpu_physical_memory_write(SH7750_BCR2_A7,&bcr2,2); I pushed this patch but it looks like there may be an endianness problem here. Cheers