[Qemu-devel] tcg/arm fixes and improvements

[Qemu-devel] tcg/arm fixes and improvements

[Aurelien Jarno]

This patch series fix a bug in div2/divu2 ops, implement setcond
and setcond2 ops and improve brcond/setcond by allowing immediate 
constants.

I have tested it using a modified version of target-mips/translate.c 
which includes setcond ops, and running mips-linux-user binaries. The 
first fixes was actually necessary to run such binaries. This has been
done with cpu-exec.c compiled with -O0 due to a bug (see my other mail).

[Qemu-devel] [PATCH 1/4] tcg/arm: fix div2/divu2

[Aurelien Jarno]

When restoring register values, increase the stack register for skipped
values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/arm/tcg-target.c |   30 ++++++++++++++++++++++++------
 1 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index f8d626d..7bdfda9 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -851,23 +851,41 @@ static void tcg_out_div_helper(TCGContext *s, int cond, const TCGArg *args,
     tcg_out_dat_reg(s, cond, ARITH_MOV, div_reg, 0, 8, SHIFT_IMM_LSL(0));
 
     /* ldr r0, [sp], #4 */
-    if (rem_reg != 0 && div_reg != 0)
+    if (rem_reg != 0 && div_reg != 0) {
         tcg_out32(s, (cond << 28) | 0x04bd0004);
+    } else {
+        tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4);
+    }
     /* ldr r1, [sp], #4 */
-    if (rem_reg != 1 && div_reg != 1)
+    if (rem_reg != 1 && div_reg != 1) {
         tcg_out32(s, (cond << 28) | 0x04bd1004);
+    } else {
+        tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4);
+    }
     /* ldr r2, [sp], #4 */
-    if (rem_reg != 2 && div_reg != 2)
+    if (rem_reg != 2 && div_reg != 2) {
         tcg_out32(s, (cond << 28) | 0x04bd2004);
+    } else {
+        tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4);
+    }
     /* ldr r3, [sp], #4 */
-    if (rem_reg != 3 && div_reg != 3)
+    if (rem_reg != 3 && div_reg != 3) {
         tcg_out32(s, (cond << 28) | 0x04bd3004);
+    } else {
+        tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4);
+    }
     /* ldr ip, [sp], #4 */
-    if (rem_reg != 12 && div_reg != 12)
+    if (rem_reg != 12 && div_reg != 12) {
         tcg_out32(s, (cond << 28) | 0x04bdc004);
+    } else {
+        tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4);
+    }
     /* ldr lr, [sp], #4 */
-    if (rem_reg != 14 && div_reg != 14)
+    if (rem_reg != 14 && div_reg != 14) {
         tcg_out32(s, (cond << 28) | 0x04bde004);
+    } else {
+        tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 4);
+    }
 }
 
 #ifdef CONFIG_SOFTMMU
-- 
1.7.0

[Qemu-devel] [PATCH 2/4] tcg/arm: implement setcond

[Aurelien Jarno]

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/arm/tcg-target.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 7bdfda9..9a76ecb 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1531,6 +1531,14 @@ static inline void tcg_out_op(TCGContext *s, int opc,
                         args[0], args[2], SHIFT_IMM_LSL(0));
         tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
         break;
+    case INDEX_op_setcond_i32:
+        tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
+                        args[1], args[2], SHIFT_IMM_LSL(0));
+        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
+                        ARITH_MOV, args[0], 0, 1);
+        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
+                        ARITH_MOV, args[0], 0, 0);
+        break;
 
     case INDEX_op_qemu_ld8u:
         tcg_out_qemu_ld(s, COND_AL, args, 0);
@@ -1629,6 +1637,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_sar_i32, { "r", "r", "ri" } },
 
     { INDEX_op_brcond_i32, { "r", "r" } },
+    { INDEX_op_setcond_i32, { "r", "r", "r" } },
 
     /* TODO: "r", "r", "r", "r", "ri", "ri" */
     { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
-- 
1.7.0

[Qemu-devel] [PATCH 3/4] tcg/arm: implement setcond2

[Aurelien Jarno]

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/arm/tcg-target.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 9a76ecb..d743dbc 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1539,6 +1539,16 @@ static inline void tcg_out_op(TCGContext *s, int opc,
         tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
                         ARITH_MOV, args[0], 0, 0);
         break;
+    case INDEX_op_setcond2_i32:
+        /* See brcond2_i32 comment */
+        tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
+                        args[2], args[4], SHIFT_IMM_LSL(0));
+        tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
+                        args[1], args[3], SHIFT_IMM_LSL(0));
+        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
+                        ARITH_MOV, args[0], 0, 1);
+        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
+                        ARITH_MOV, args[0], 0, 0);
 
     case INDEX_op_qemu_ld8u:
         tcg_out_qemu_ld(s, COND_AL, args, 0);
@@ -1643,6 +1653,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
     { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
     { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
+    { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
 
     { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
     { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
-- 
1.7.0

[Qemu-devel] [PATCH 4/4] tcg/arm: accept immediate arguments for brcond/setcond

[Aurelien Jarno]

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/arm/tcg-target.c |   26 ++++++++++++++++++++------
 1 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index d743dbc..63f84c3 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1512,8 +1512,15 @@ static inline void tcg_out_op(TCGContext *s, int opc,
         break;
 
     case INDEX_op_brcond_i32:
-        tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
-                        args[0], args[1], SHIFT_IMM_LSL(0));
+        if (const_args[1]) {
+            int rot;
+            rot = encode_imm(args[1]);
+            tcg_out_dat_imm(s, COND_AL, ARITH_CMP,
+                            0, args[0], rotl(args[1], rot) | (rot << 7));
+        } else {
+            tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
+                            args[0], args[1], SHIFT_IMM_LSL(0));
+        }
         tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
         break;
     case INDEX_op_brcond2_i32:
@@ -1532,8 +1539,15 @@ static inline void tcg_out_op(TCGContext *s, int opc,
         tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
         break;
     case INDEX_op_setcond_i32:
-        tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
-                        args[1], args[2], SHIFT_IMM_LSL(0));
+        if (const_args[2]) {
+            int rot;
+            rot = encode_imm(args[2]);
+            tcg_out_dat_imm(s, COND_AL, ARITH_CMP,
+                            0, args[1], rotl(args[2], rot) | (rot << 7));
+        } else {
+            tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
+                            args[1], args[2], SHIFT_IMM_LSL(0));
+        }
         tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
                         ARITH_MOV, args[0], 0, 1);
         tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
@@ -1646,8 +1660,8 @@ static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
     { INDEX_op_sar_i32, { "r", "r", "ri" } },
 
-    { INDEX_op_brcond_i32, { "r", "r" } },
-    { INDEX_op_setcond_i32, { "r", "r", "r" } },
+    { INDEX_op_brcond_i32, { "r", "rI" } },
+    { INDEX_op_setcond_i32, { "r", "r", "rI" } },
 
     /* TODO: "r", "r", "r", "r", "ri", "ri" */
     { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
-- 
1.7.0

Re: [Qemu-devel] tcg/arm fixes and improvements

[andrzej zaborowski]

On 1 March 2010 22:33, Aurelien Jarno <aurelien@aurel32.net> wrote:
> This patch series fix a bug in div2/divu2 ops, implement setcond
> and setcond2 ops and improve brcond/setcond by allowing immediate
> constants.

Thanks, pushed the four changes + added a missing break after
setcond2.  I'm not totally sure but I think setcond can be shortened
to two instructions for each case or some cases, the COND_NE case
could look like:

subs dest, t1, t2
movne dest, #1

and the lesser/greater cases can use the carry flag and "adc".

Cheers