Re: [PATCH v11 08/46] target/mips: Add emulation of nanoMIPS 16-bit branch instructions

[Faraz Shahbazker <faraz.shahbazker@gmail.com>]

On 5/29/21 7:22 PM, Philippe Mathieu-Daudé wrote:
> On Mon, Aug 20, 2018 at 8:17 PM Aleksandar Markovic
> <aleksandar.markovic@rt-rk.com> wrote:
>>
>> From: Stefan Markovic <smarkovic@wavecomp.com>
>>
>> Add emulation of nanoMIPS 16-bit branch instructions.
>> ...
>> +        /* Compare two registers */
>> +        case OPC_BPOSGE32:
>> +            tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
> 
> This opcode implementation seems incomplete, per the ISA manual:
> 
> If a control transfer instruction (CTI) is executed in the forbidden
> slot of a branch or jump, Release 6 implementations are required to
> signal a Reserved Instruction Exception. A CTI is considered to be one
> of the following instructions: branch, jump, NAL (Release 6), ERET,
> ERETNC (Release 5), DERET, WAIT, or PAUSE (Release 2). An instruction
> is in the forbidden slot if it is the instruction following the
> branch.
> 

This also stems from mistakes in the DSP instruction manual. The 
description text for BPOSGE32C in the nanoMIPS32 DSP manual has been 
blindly copy pasted from microMIPS32 DSP manual. As per the nanoMIPS32 
Instruction Set Technical Reference Manual, Revision 1.01, Chapter 1, 
Introduction, p12 [1] :

"branch delay slots and forbidden slots have been removed."

[1] 
https://s3-eu-west-1.amazonaws.com/downloads-mips/I7200/I7200+product+launch/MIPS_nanomips32_ISA_TRM_01_01_MD01247.pdf

The nanoMIPS architecture is not a revision of MIPS release 6, but an 
entirely new architecture that happens to have a lot in common with MIPS 
release 6. Using the same target sources to implement both means we get 
quite a bit of code reuse, but also that we have to be cognizant of such 
differences.

- farazS