[Qemu-devel] [Bug?] in powerPc board uic emulation

[Qemu-devel] [Bug?] in powerPc board uic emulation

[Salvatore Lionetti]

Hi,

i've added new board latest svn snapshot, updated few ours ago, with 450GPe cpu but got some pb, almost resolved.
The last, i hope, is that 'internal' interrupt line 11, polarity high, level triggered, destinated to MAL TX End of Buffer (TXEOB0), seem to persist after managed.

I've tested with qemu-0.9.1 and all is ok.
Since i've noted that uic device code is changed, before explain pb at u-boot side, i'd like to check 'internally'.

In detail this link the driver code, from u-boot-1.1.6:
http://svn.neurostechnology.com/filedetails.php?repname=neuros-bsp&path=%2Ftrunk%2Fbootloader%2Fcpu%2Fppc4xx%2F4xx_enet.c&rev=39&sc=0
The interrupt management is centralized in 2nd function named enetInt().

Have a good day


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Re: [Qemu-devel] [Bug?] in powerPc board uic emulation

[Hollis Blanchard]

On Thu, Nov 13, 2008 at 7:04 PM, Salvatore Lionetti
<salvatorelionetti@yahoo.it> wrote:
> Hi,
>
> i've added new board latest svn snapshot, updated few ours ago, with 450GPe cpu but got some pb, almost resolved.
> The last, i hope, is that 'internal' interrupt line 11, polarity high, level triggered, destinated to MAL TX End of Buffer (TXEOB0), seem to persist after managed.

Without seeing your revised patch, it's difficult to guess. However,
in the original patch you did post you are doing something strange
like this:

+#define INTN(a) (31-a)
...
+    mal_irqs[0] = pic[INTN(14)];
+
     ppc405_mal_init(env, mal_irqs);

> I've tested with qemu-0.9.1 and all is ok.
> Since i've noted that uic device code is changed, before explain pb at u-boot side, i'd like to check 'internally'.

One UIC change between 0.9.1 and now is that the IRQ numbers were
"inverted" (31-n) to match the documentation. I don't have the 405EP
user manual handy to check, but I suspect you wrote your INTN macro to
do the same thing, and you're now inverting them twice.

See http://svn.savannah.gnu.org/viewvc/trunk/hw/ppc4xx_devs.c?root=qemu&r1=3726&r2=4273

Thanks for updating your patch. Have you also corrected the endianness
issues you mentioned in the first draft, so that it can work on
big-endian hosts?

-Hollis