From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L9Ln3-0007DS-9X for qemu-devel@nongnu.org; Sun, 07 Dec 2008 10:43:25 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L9Lmz-0007C1-5U for qemu-devel@nongnu.org; Sun, 07 Dec 2008 10:43:24 -0500 Received: from [199.232.76.173] (port=49964 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L9Lmy-0007Bx-TY for qemu-devel@nongnu.org; Sun, 07 Dec 2008 10:43:20 -0500 Received: from yx-out-1718.google.com ([74.125.44.158]:20478) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L9Lmx-0003lL-Su for qemu-devel@nongnu.org; Sun, 07 Dec 2008 10:43:20 -0500 Received: by yx-out-1718.google.com with SMTP id 3so497145yxi.82 for ; Sun, 07 Dec 2008 07:43:15 -0800 (PST) Message-ID: Date: Sun, 7 Dec 2008 09:43:14 -0600 From: "Hollis Blanchard" Sender: slightlyunconventional@gmail.com Subject: Re: [Qemu-devel] PowerPC reset vector? In-Reply-To: <20081207140239.GU4440@hall.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20081207140239.GU4440@hall.aurel32.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Laurent Vivier On Sun, Dec 7, 2008 at 8:02 AM, Aurelien Jarno wrote: > On Sun, Dec 07, 2008 at 02:58:40PM +0200, Blue Swirl wrote: >> Hi, > Hi! > >> Currently PPC hard reset vector is 0xfffffffc for most cases. I can't >> find this vector in the few PPC docs I have. Instead all docs point to >> 0x00100 + base, where base can be 0xfff00000 or zero. Is the vector >> correct? > > According to the PowerISA manual, the reset exception vector is the one > you define. However on power-up, the CPU does not jump to the reset > exception vector but instead: > - initialize msr > - empty all TLB > - create a boot TLB that maps the last 4kB page in the implemented > effective storage address space that maps to the last 4kB page of the > physical address space > - start execution of instruction at the last word address of the page > mapped by the boot TLB entry. Hang on, that's not the whole story. There are a number of supervisor-level difference between server (now called "Book III-S") and embedded ("Book III-E") PowerPC, and this is one of them. The behavior you describe is true for Book E, and also happens to be true for 405 (which predates Book E and is not similar in other respects). However, it is *not* true for "classic" or "server" PowerPC, such as 604 or 970. Those processors reset as Blue described, with the NIP at 0xfff00100. (Actually, I think some may do even different things, like start at 0xfff00000, but I'm not sure.) Since qemu emulates both types of PowerPC, the reset vector must not be hardcoded. -Hollis