From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N9RqA-0003Nw-Tk for qemu-devel@nongnu.org; Sat, 14 Nov 2009 18:15:34 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N9Rq5-0003Ka-Gv for qemu-devel@nongnu.org; Sat, 14 Nov 2009 18:15:33 -0500 Received: from [199.232.76.173] (port=60241 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N9Rq5-0003KS-9Y for qemu-devel@nongnu.org; Sat, 14 Nov 2009 18:15:29 -0500 Received: from mail-yw0-f176.google.com ([209.85.211.176]:51317) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N9Rq4-0005h3-VU for qemu-devel@nongnu.org; Sat, 14 Nov 2009 18:15:29 -0500 Received: by ywh6 with SMTP id 6so3777046ywh.4 for ; Sat, 14 Nov 2009 15:15:28 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: From: Artyom Tarasenko Date: Sun, 15 Nov 2009 00:15:08 +0100 Message-ID: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] Re: [PATCH] sparc32 irq clearing (guest Solaris performance+NetBSD) fix List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel 2009/11/14 Blue Swirl : > On Sat, Nov 14, 2009 at 3:03 AM, Artyom Tarasenko > wrote: >> According to NCR89C105 documentation >> http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C10= 5.txt >> >> Interrupts are cleared by disabling and then re-enabling them. >> This patch implements the specified behaviour. The most visible effects: > > I think the current version also implements this behaviour. The > difference is that now we clear on disable, with your version, the > interrupts are cleared when re-enabling them. Doesn't this imply that the current version does not implement this ("Interrupts are cleared by disabling and then re-enabling them") behavior?= ;-) > With the current version, the interrupts which arrived after getting > cleared during disable but before re-enabling become visible after > re-enabling. It looks like esp driver in Aurora 1.0, 2.0 and 2.1 > depend on this. Hm. It certainly makes sense. But I don't see how does it agree with the NCR89C105 docs. Can it be the documentation is not precise? >> - NetBSD 1.3.3 - 1.5.3 boots successfully > > I didn't find those even on ftp.netbsd.org, the first I have is 1.6. > Thus I could not test if any of the changes I did had any positive > effect except if some test failed. Have you looked in the NetBSD-archive at ftp.netbsd.org? ftp://ftp.netbsd.org/pub/NetBSD/NetBSD-archive/ >> - Solaris 2.5.1 - 7 boots ~1500 times faster (~20 seconds instead of ~8 = hours) >> >> Signed-off-by: Artyom Tarasenko >> --- >> diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c >> index 9680392..779c661 100644 >> --- a/hw/slavio_intctl.c >> +++ b/hw/slavio_intctl.c >> @@ -177,19 +177,19 @@ static void slavio_intctlm_mem_writel(void >> *opaque, target_phys_addr_t addr, >> =A0 =A0 saddr =3D addr >> 2; >> =A0 =A0 DPRINTF("write system reg 0x" TARGET_FMT_plx " =3D %x\n", addr, = val); >> =A0 =A0 switch (saddr) { >> - =A0 =A0case 2: // clear (enable) >> + =A0 =A0case 2: // clear (enable, clear formerly disabled pending) >> =A0 =A0 =A0 =A0 // Force clear unused bits >> =A0 =A0 =A0 =A0 val &=3D MASTER_IRQ_MASK; >> + =A0 =A0 =A0 =A0s->intregm_pending &=3D (s->intregm_disabled & val); > > This looks buggy, the AND operation will clear a lot of bits unrelated > to val. I think you are missing a ~ here. I tried a few combinations, > but none of them passed my tests. My bad. It had to be s->intregm_pending &=3D ~(s->intregm_disabled & val) . But unfortunately it doesn't work. >> =A0 =A0 =A0 =A0 s->intregm_disabled &=3D ~val; >> =A0 =A0 =A0 =A0 DPRINTF("Enabled master irq mask %x, curmask %x\n", val, >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 s->intregm_disabled); >> =A0 =A0 =A0 =A0 slavio_check_interrupts(s, 1); >> =A0 =A0 =A0 =A0 break; >> - =A0 =A0case 3: // set (disable, clear pending) >> + =A0 =A0case 3: // set (disable, do not clear pending) >> =A0 =A0 =A0 =A0 // Force clear unused bits >> =A0 =A0 =A0 =A0 val &=3D MASTER_IRQ_MASK; >> =A0 =A0 =A0 =A0 s->intregm_disabled |=3D val; >> - =A0 =A0 =A0 =A0s->intregm_pending &=3D ~val; > > Here > s->intregm_pending &=3D ~s->intregm_disabled; > would also pass my tests. Does that change anything? No, doesn't work for me either. Also I put some additional printfs into sun4m.c and see that interrupts are both set while being already set, and reset while not being = set. Looks like a bug? static void cpu_set_irq(void *opaque, int irq, int level) { CPUState *env =3D opaque; if (level) { DPRINTF("Raise CPU IRQ %d\n", irq); env->halted =3D 0; if(env->pil_in & (1 << irq)) {printf("already set: %d\n",irq);retur= n;} env->pil_in |=3D 1 << irq; cpu_check_irqs(env); } else { DPRINTF("Lower CPU IRQ %d\n", irq); if(~(env->pil_in & (1 << irq))) {printf("already low: %d\n",irq);return;} env->pil_in &=3D ~(1 << irq); cpu_check_irqs(env); } }