From: Artyom Tarasenko <atar4qemu@googlemail.com>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] Re: [PATCH] sparc32 irq clearing (guest Solaris performance+NetBSD) fix
Date: Fri, 15 Jan 2010 23:37:49 +0100 [thread overview]
Message-ID: <fb8d4f71001151437w54b1ecddtba0acdb9eeb716a5@mail.gmail.com> (raw)
In-Reply-To: <f43fc5580911171245o4bb07f2ekd134fbbf3fb33fe4@mail.gmail.com>
after running some OBP/forth tests on a real SS-20 I must say that
most of our (especially my) speculations were wrong, as well as what
is written in
http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt :
1. SS-20 may loose interrupts. At least if a timer interrupt was lowered while
still being masked, it is not triggered when enabled.
2. Neither masking, nor unmasking interrupt clears pending bits in the
status register. NCR89C105.txt claims it should, but
Sun4M_SystemArchitecture_edited2.pdf doesn't. I guess the later one is
more reliable.
--
Regards,
Artyom Tarasenko
solaris/sparc under qemu blog: http://tyom.blogspot.com/
next prev parent reply other threads:[~2010-01-15 22:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-11-14 1:03 [Qemu-devel] [PATCH] sparc32 irq clearing (guest Solaris performance+NetBSD) fix Artyom Tarasenko
2009-11-14 15:26 ` [Qemu-devel] " Blue Swirl
2009-11-14 23:15 ` Artyom Tarasenko
2009-11-15 22:13 ` Blue Swirl
2009-11-16 11:47 ` Artyom Tarasenko
2009-11-16 16:14 ` Blue Swirl
2009-11-16 17:19 ` Artyom Tarasenko
2009-11-16 21:53 ` Blue Swirl
2009-11-16 22:31 ` Jamie Lokier
2009-11-16 22:50 ` Artyom Tarasenko
2009-11-16 22:35 ` Jamie Lokier
2009-11-16 22:44 ` Artyom Tarasenko
2009-11-17 20:45 ` Blue Swirl
2010-01-15 22:37 ` Artyom Tarasenko [this message]
2009-11-16 16:45 ` Artyom Tarasenko
2009-11-16 22:27 ` Jamie Lokier
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