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From: Artyom Tarasenko <atar4qemu@googlemail.com>
Date: Fri, 15 Jan 2010 23:37:49 +0100
Message-ID: <fb8d4f71001151437w54b1ecddtba0acdb9eeb716a5@mail.gmail.com>
Subject: Re: [Qemu-devel] Re: [PATCH] sparc32 irq clearing (guest Solaris
	performance+NetBSD) fix
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To: Blue Swirl <blauwirbel@gmail.com>
Cc: qemu-devel <qemu-devel@nongnu.org>

after running some OBP/forth tests on a real SS-20 I must say that
most of our (especially my) speculations were wrong, as well as what
is written in
http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt :

1. SS-20 may loose interrupts. At least if a timer interrupt was lowered while
still being masked, it is not triggered when enabled.

2. Neither masking, nor unmasking interrupt clears pending bits in the
status register. NCR89C105.txt claims it should, but
Sun4M_SystemArchitecture_edited2.pdf doesn't. I guess the later one is
more reliable.

-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/