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From: David Hildenbrand <david@redhat.com>
To: Thomas Huth <thuth@redhat.com>, qemu-devel@nongnu.org
Cc: Janosch Frank <frankja@linux.ibm.com>,
	Cornelia Huck <cohuck@redhat.com>,
	Halil Pasic <pasic@linux.ibm.com>,
	Christian Borntraeger <borntraeger@de.ibm.com>,
	qemu-s390x@nongnu.org, Richard Henderson <rth@twiddle.net>
Subject: Re: [PATCH v1 1/5] s390x/mmu: Add EDAT2 translation support
Date: Tue, 1 Oct 2019 10:51:20 +0200	[thread overview]
Message-ID: <fc003b6e-a38c-ced7-0c84-a64ebc26e91b@redhat.com> (raw)
In-Reply-To: <26665f90-e821-c103-0178-7c1ca51de647@redhat.com>

On 01.10.19 10:41, Thomas Huth wrote:
> On 26/09/2019 12.18, David Hildenbrand wrote:
>> On 26.09.19 12:16, David Hildenbrand wrote:
>>> This only adds basic support to the DAT translation, but no EDAT2 support
>>> for TCG. E.g., the gdbstub under kvm uses this function, too, to
>>> translate virtual addresses.
>>>
>>> Reviewed-by: Thomas Huth <thuth@redhat.com>
>>> Signed-off-by: David Hildenbrand <david@redhat.com>
>>> ---
>>>  target/s390x/mmu_helper.c | 9 +++++++++
>>>  1 file changed, 9 insertions(+)
>>>
>>> diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
>>> index 6b34c4c7b4..54f54137ec 100644
>>> --- a/target/s390x/mmu_helper.c
>>> +++ b/target/s390x/mmu_helper.c
>>> @@ -120,6 +120,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
>>>  {
>>>      const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
>>>                         s390_has_feat(S390_FEAT_EDAT);
>>> +    const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2);
>>>      const int asce_tl = asce & ASCE_TABLE_LENGTH;
>>>      const int asce_p = asce & ASCE_PRIVATE_SPACE;
>>>      hwaddr gaddr = asce & ASCE_ORIGIN;
>>> @@ -219,9 +220,17 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
>>>          if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
>>>              return PGM_TRANS_SPEC;
>>>          }
>>> +        if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) {
>>> +            return PGM_TRANS_SPEC;
>>> +        }
>>>          if (edat1 && (entry & REGION_ENTRY_P)) {
>>>              *flags &= ~PAGE_WRITE;
>>>          }
>>> +        if (edat2 && (entry & REGION3_ENTRY_FC)) {
>>> +            *raddr = (entry & REGION3_ENTRY_RFAA) |
>>> +                     (vaddr & REGION3_ENTRY_RFAA);
>>
>> Messed up
>>
>> (vaddr & ~REGION3_ENTRY_RFAA)
>>
>> it is.
> 
> With that fix:
> 
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> 

BTW, this change explains the different order of checks you mentioned. I now have here:

diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index dc33c63b1d..dcbffb682f 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -120,6 +120,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
 {
     const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
                        s390_has_feat(S390_FEAT_EDAT);
+    const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2);
     const int asce_tl = asce & ASCE_TABLE_LENGTH;
     const int asce_p = asce & ASCE_PRIVATE_SPACE;
     hwaddr gaddr = asce & ASCE_ORIGIN;
@@ -217,6 +218,17 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
         if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
             return PGM_TRANS_SPEC;
         }
+        if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) {
+            return PGM_TRANS_SPEC;
+        }
+        if (edat2 && (entry & REGION3_ENTRY_FC)) {
+            if (entry & REGION_ENTRY_P) {
+                *flags &= ~PAGE_WRITE;
+            }
+            *raddr = (entry & REGION3_ENTRY_RFAA) |
+                     (vaddr & ~REGION3_ENTRY_RFAA);
+            return 0;
+        }
         if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
             VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
             return PGM_SEGMENT_TRANS;


-- 

Thanks,

David / dhildenb


  reply	other threads:[~2019-10-01  8:54 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-26 10:16 [PATCH v1 0/5] s390x/mmu: Implement more facilities David Hildenbrand
2019-09-26 10:16 ` [PATCH v1 1/5] s390x/mmu: Add EDAT2 translation support David Hildenbrand
2019-09-26 10:18   ` David Hildenbrand
2019-10-01  8:41     ` Thomas Huth
2019-10-01  8:51       ` David Hildenbrand [this message]
2019-10-01  8:55         ` Thomas Huth
2019-10-01  8:56           ` David Hildenbrand
2019-09-26 10:16 ` [PATCH v1 2/5] s390x/mmu: Implement ESOP-2 and access-exception-fetch/store-indication facility David Hildenbrand
2019-09-27 12:30   ` David Hildenbrand
2019-10-01  8:48     ` Thomas Huth
2019-09-26 10:16 ` [PATCH v1 3/5] s390x/mmu: Implement Instruction-Execution-Protection Facility David Hildenbrand
2019-10-01  9:06   ` Thomas Huth
2019-09-26 10:16 ` [PATCH v1 4/5] s390x/cpumodel: Prepare for changes of QEMU model David Hildenbrand
2019-09-26 10:16 ` [PATCH v1 5/5] s390x/cpumodel: Add new TCG features to QEMU cpu model David Hildenbrand
2019-10-07 17:00   ` Cornelia Huck
2019-10-04 13:23 ` [PATCH v1 0/5] s390x/mmu: Implement more facilities David Hildenbrand
2019-10-07 17:02   ` Cornelia Huck
2019-10-09 10:33     ` David Hildenbrand

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