From: Richard Henderson <richard.henderson@linaro.org>
To: "Bibo Mao" <maobibo@loongson.cn>,
"Song Gao" <gaosong@loongson.cn>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH v3 03/12] target/loongarch: Reduce TLB flush with helper_tlbwr
Date: Wed, 3 Sep 2025 15:07:58 +0200 [thread overview]
Message-ID: <fc0eaa0c-252e-4c74-8a2c-ddf0f3b11bb4@linaro.org> (raw)
In-Reply-To: <20250903084827.3085911-4-maobibo@loongson.cn>
On 9/3/25 10:48, Bibo Mao wrote:
> With function helper_tlbwr(), specified LoongArch TLB entry will be
> updated. There are two PTE pages in one TLB entry called even/odd
> pages. Supposing even/odd page is normal/none state, when odd page
> is added, TLB entry is changed as normal/normal state and even page
> keeps unchanged.
>
> In this situation, it is not necessary to flush QEMU TLB since even
> page keep unchanged and odd page is newly changed. Here check whether
> PTE page is the same or not, TLB flush can be skipped if both are the
> same or newly added.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> target/loongarch/tcg/tlb_helper.c | 33 ++++++++++++++++++++++++++-----
> 1 file changed, 28 insertions(+), 5 deletions(-)
>
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index fcd03ca320..331b485b1a 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -302,16 +302,39 @@ void helper_tlbrd(CPULoongArchState *env)
> void helper_tlbwr(CPULoongArchState *env)
> {
> int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
> + LoongArchTLB *old, new;
Perhaps "new = { }", then ...
> + new.tlb_misc = 0;
> + new.tlb_entry0 = 0;
> + new.tlb_entry1 = 0;
... this is unnecessary.
> + fill_tlb_entry(env, &new);
> + /* Check whether ASID/VPPN is the same */
> + if (old->tlb_misc == new.tlb_misc) {
> + /* Check whether both even/odd pages is the same or invalid */
> + tlb_v0 = FIELD_EX64(old->tlb_entry0, TLBENTRY, V);
> + tlb_v1 = FIELD_EX64(old->tlb_entry1, TLBENTRY, V);
> + if ((!tlb_v0 || new.tlb_entry0 == old->tlb_entry0) &&
> + (!tlb_v1 || new.tlb_entry1 == old->tlb_entry1)) {
> + skip_inv = true;
> + }
> + }
> +
> + /* flush tlb before updating the entry */
> + if (!skip_inv) {
> + invalidate_tlb(env, index);
> + }
> + old->tlb_misc = new.tlb_misc;
> + old->tlb_entry0 = new.tlb_entry0;
> + old->tlb_entry1 = new.tlb_entry1;
Perhaps better as "*old = new".
Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2025-09-03 13:08 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-03 8:48 [PATCH v3 00/12] target/loongarch: Small enhancement about TLB flush Bibo Mao
2025-09-03 8:48 ` [PATCH v3 01/12] target/loongarch: Use mmu idx bitmap method when flush TLB Bibo Mao
2025-09-03 13:02 ` Richard Henderson
2025-09-04 7:23 ` Bibo Mao
2025-09-03 8:48 ` [PATCH v3 02/12] target/loongarch: Add parameter tlb pointer with fill_tlb_entry Bibo Mao
2025-09-03 8:48 ` [PATCH v3 03/12] target/loongarch: Reduce TLB flush with helper_tlbwr Bibo Mao
2025-09-03 13:07 ` Richard Henderson [this message]
2025-09-04 7:28 ` Bibo Mao
2025-09-03 8:48 ` [PATCH v3 04/12] target/loongarch: Update TLB index selection method Bibo Mao
2025-09-03 13:09 ` Richard Henderson
2025-09-03 8:48 ` [PATCH v3 05/12] target/loongarch: Fix page size set issue with CSR_STLBPS Bibo Mao
2025-09-03 8:48 ` [PATCH v3 06/12] target/loongarch: Add tlb search callback in loongarch_tlb_search() Bibo Mao
2025-09-03 13:14 ` Richard Henderson
2025-09-04 7:46 ` Bibo Mao
2025-09-03 8:48 ` [PATCH v3 07/12] target/loongarch: Add common API loongarch_tlb_search_cb() Bibo Mao
2025-09-03 13:16 ` Richard Henderson
2025-09-03 8:48 ` [PATCH v3 08/12] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_g Bibo Mao
2025-09-03 13:20 ` Richard Henderson
2025-09-04 9:17 ` Bibo Mao
2025-09-03 8:48 ` [PATCH v3 09/12] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid Bibo Mao
2025-09-03 13:21 ` Richard Henderson
2025-09-04 9:52 ` Bibo Mao
2025-09-03 8:48 ` [PATCH v3 10/12] target/loongarch: Invalid tlb entry in invalidate_tlb() Bibo Mao
2025-09-03 13:00 ` Richard Henderson
2025-09-04 10:04 ` Bibo Mao
2025-09-03 8:53 ` [PATCH v3 11/12] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g() Bibo Mao
2025-09-03 12:56 ` Richard Henderson
2025-09-03 8:54 ` [PATCH v3 12/12] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid() Bibo Mao
2025-09-03 12:56 ` Richard Henderson
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