From: Richard Henderson <richard.henderson@linaro.org>
To: Robert Hoo <robert.hu@linux.intel.com>,
pbonzini@redhat.com, ehabkost@redhat.com
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v3] i386/cpu_dump: support AVX512 ZMM regs dump
Date: Wed, 24 Mar 2021 07:44:17 -0600 [thread overview]
Message-ID: <fc15756c-755d-fc96-80f4-ac9d6f6b461b@linaro.org> (raw)
In-Reply-To: <1616572804-7898-1-git-send-email-robert.hu@linux.intel.com>
On 3/24/21 2:00 AM, Robert Hoo wrote:
> + if ((env->xcr0 & XFEATURE_AVX512) == XFEATURE_AVX512) {
> + /* XSAVE enabled AVX512 */
> + nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
> + for (i = 0; i < nb; i++) {
> + qemu_fprintf(f, "ZMM%02d=0x%016lx %016lx %016lx %016lx %016lx "
> + "%016lx %016lx %016lx\n",
> + i,
> + env->xmm_regs[i].ZMM_Q(7),
> + env->xmm_regs[i].ZMM_Q(6),
> + env->xmm_regs[i].ZMM_Q(5),
> + env->xmm_regs[i].ZMM_Q(4),
> + env->xmm_regs[i].ZMM_Q(3),
> + env->xmm_regs[i].ZMM_Q(2),
> + env->xmm_regs[i].ZMM_Q(1),
> + env->xmm_regs[i].ZMM_Q(0));
> + }
Dump opmask regs?
> + } else if (env->xcr0 & XFEATURE_AVX) {
This is normally a 2-bit test.
> + /* XSAVE enabled AVX */
> + nb = env->hflags & HF_CS64_MASK ? 16 : 8;
> + for (i = 0; i < nb; i++) {
> + qemu_fprintf(f, "YMM%02d=0x%016lx %016lx %016lx %016lx\n",
> + i,
> + env->xmm_regs[i].ZMM_Q(3),
> + env->xmm_regs[i].ZMM_Q(2),
> + env->xmm_regs[i].ZMM_Q(1),
> + env->xmm_regs[i].ZMM_Q(0));
> + }
> + } else { /* SSE and below cases */
> + nb = env->hflags & HF_CS64_MASK ? 16 : 8;
> + for (i = 0; i < nb; i++) {
> + qemu_fprintf(f, "XMM%02d=0x%016lx %016lx",
> + i,
> + env->xmm_regs[i].ZMM_Q(1),
> + env->xmm_regs[i].ZMM_Q(0));
> + if ((i & 1) == 1)
> + qemu_fprintf(f, "\n");
> + else
> + qemu_fprintf(f, " ");
I'd be tempted to merge that second printf into the first, with "%s" and (i & 1
? "\n" : " "). Otherwise you'll need to add braces to that IF to satisfy
checkpatch.
> +#define XFEATURE_X87 (1UL << 0)
> +#define XFEATURE_SSE (1UL << 1)
> +#define XFEATURE_AVX (1UL << 2)
> +#define XFEATURE_AVX512_OPMASK (1UL << 5)
> +#define XFEATURE_AVX512_ZMM_Hi256 (1UL << 6)
> +#define XFEATURE_AVX512_Hi16_ZMM (1UL << 7)
> +#define XFEATURE_AVX512 (XFEATURE_AVX512_OPMASK | \
> + XFEATURE_AVX512_ZMM_Hi256 | \
> + XFEATURE_AVX512_Hi16_ZMM)
Except for the last, these already exist under the name XSTATE_*_MASK.
I think you can just as well declare local variables to hold the 3 bits for the
avx512 test and the 2 bits for the avx test.
r~
next prev parent reply other threads:[~2021-03-24 13:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-24 8:00 [PATCH v3] i386/cpu_dump: support AVX512 ZMM regs dump Robert Hoo
2021-03-24 13:44 ` Richard Henderson [this message]
2021-03-25 3:15 ` Robert Hoo
2021-03-25 12:39 ` Richard Henderson
2021-03-26 1:47 ` Robert Hoo
2021-03-26 13:11 ` Richard Henderson
2021-03-26 14:16 ` Robert Hoo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=fc15756c-755d-fc96-80f4-ac9d6f6b461b@linaro.org \
--to=richard.henderson@linaro.org \
--cc=ehabkost@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=robert.hu@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).