From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60282) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1axHqk-0005cq-A4 for qemu-devel@nongnu.org; Mon, 02 May 2016 13:41:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1axHqY-0000AA-OS for qemu-devel@nongnu.org; Mon, 02 May 2016 13:41:32 -0400 Received: from mail-qg0-x242.google.com ([2607:f8b0:400d:c04::242]:33556) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1axHqX-000059-Hl for qemu-devel@nongnu.org; Mon, 02 May 2016 13:41:26 -0400 Received: by mail-qg0-x242.google.com with SMTP id 90so5873752qgz.0 for ; Mon, 02 May 2016 10:41:11 -0700 (PDT) Sender: Richard Henderson References: <1462210518-26522-1-git-send-email-sergey.fedorov@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 2 May 2016 07:41:02 -1000 MIME-Version: 1.0 In-Reply-To: <1462210518-26522-1-git-send-email-sergey.fedorov@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] fixup! tcg/mips: Make direct jump patching thread-safe List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Fedorov , qemu-devel@nongnu.org Cc: Sergey Fedorov , Aurelien Jarno On 05/02/2016 07:35 AM, Sergey Fedorov wrote: > From: Sergey Fedorov > > Signed-off-by: Sergey Fedorov > Signed-off-by: Sergey Fedorov > --- > > This patch is based on a commit: > > e601ccb62016 ("cpu-exec: Move TB chaining into tb_find_fast()") > > from: > > https://github.com/rth7680/qemu.git tcg-next > > tcg/mips/tcg-target.inc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c > index b0440b9c5a79..50e98ea63a73 100644 > --- a/tcg/mips/tcg-target.inc.c > +++ b/tcg/mips/tcg-target.inc.c > @@ -1885,6 +1885,6 @@ static void tcg_target_init(TCGContext *s) > > void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) > { > - atomic_set(ptr, deposit32(OPC_J, 0, 26, addr >> 2)); > + atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); > flush_icache_range(jmp_addr, jmp_addr + 4); > } > Thanks. Will fix.