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[176.171.209.234]) by smtp.gmail.com with ESMTPSA id l21-20020a1709061c5500b009ad89697c86sm2657005ejg.144.2023.09.15.09.58.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Sep 2023 09:58:00 -0700 (PDT) Message-ID: Date: Fri, 15 Sep 2023 18:57:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v2 3/3] softmmu: Introduce cpu_address_space_sync Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20230915163254.123338-1-richard.henderson@linaro.org> <20230915163254.123338-4-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230915163254.123338-4-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 15/9/23 18:32, Richard Henderson wrote: > Synchronously check and update the address space for the > current cpu for any slow path access. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1866 > Signed-off-by: Richard Henderson > --- > include/exec/memory.h | 6 ++++++ > accel/tcg/cputlb.c | 2 ++ > softmmu/physmem.c | 20 ++++++++++++++++++++ > 3 files changed, 28 insertions(+) > > diff --git a/include/exec/memory.h b/include/exec/memory.h > index 68284428f8..7ec842076f 100644 > --- a/include/exec/memory.h > +++ b/include/exec/memory.h > @@ -2780,6 +2780,12 @@ void address_space_cache_destroy(MemoryRegionCache *cache); > IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, > bool is_write, MemTxAttrs attrs); > > +/* > + * Ensure all cpu address spaces are up-to-date. > + * Return true if changes made and tlb flushed. No return value, stale comment? > + */ > +void cpu_address_space_sync(CPUState *cpu); > + > /* address_space_translate: translate an address range into an address space > * into a MemoryRegion and an address range into that section. Should be > * called from an RCU critical section, to avoid that the last reference > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index 3270f65c20..91be3f3064 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -1827,6 +1827,8 @@ static bool mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, > l->page[1].size = 0; > crosspage = (addr ^ l->page[1].addr) & TARGET_PAGE_MASK; > > + cpu_address_space_sync(env_cpu(env)); > + > if (likely(!crosspage)) { > mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); > > diff --git a/softmmu/physmem.c b/softmmu/physmem.c > index e1c535380a..5a89caa257 100644 > --- a/softmmu/physmem.c > +++ b/softmmu/physmem.c > @@ -2536,6 +2536,26 @@ static void tcg_commit(MemoryListener *listener) > } > } > > +void cpu_address_space_sync(CPUState *cpu) > +{ > + int i, n = cpu->num_ases; > + bool need_flush = false; > + > + for (i = 0; i < n; ++i) { > + CPUAddressSpace *cpuas = &cpu->cpu_ases[i]; > + uint32_t gen = qatomic_load_acquire(&cpuas->layout_gen); > + > + if (cpuas->commit_gen != gen) { > + cpuas->commit_gen = gen; > + cpuas->memory_dispatch = address_space_to_dispatch(cpuas->as); > + need_flush = true; > + } > + } > + if (need_flush) { > + tlb_flush(cpu); > + } > +} > + > static void memory_map_init(void) > { > system_memory = g_malloc(sizeof(*system_memory));