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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a099ae3d3bsm9765237f8f.33.2025.05.05.01.19.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 May 2025 01:19:09 -0700 (PDT) Message-ID: Date: Mon, 5 May 2025 10:19:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/6] hw/arm/smmuv3: Add support to associate a PCIe RC Content-Language: en-US To: Donald Dutile , Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Markus Armbruster , Peter Maydell , "Daniel P. Berrange" , =?UTF-8?Q?Alex_Benn=C3=A9e?= Cc: jgg@nvidia.com, nicolinc@nvidia.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250502102707.110516-1-shameerali.kolothum.thodi@huawei.com> <20250502102707.110516-2-shameerali.kolothum.thodi@huawei.com> <03c31d89-ad24-4470-99d0-a77e693e3ba2@redhat.com> From: Eric Auger In-Reply-To: <03c31d89-ad24-4470-99d0-a77e693e3ba2@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.411, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 5/2/25 8:16 PM, Donald Dutile wrote: > > > On 5/2/25 6:27 AM, Shameer Kolothum wrote: >> Although this change does not affect functionality at present, it lays >> the groundwork for enabling user-created SMMUv3 devices in >> future patches >> >> Signed-off-by: Shameer Kolothum >> --- >>   hw/arm/smmuv3.c | 26 ++++++++++++++++++++++++++ >>   hw/arm/virt.c   |  3 ++- >>   2 files changed, 28 insertions(+), 1 deletion(-) >> >> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c >> index ab67972353..605de9b721 100644 >> --- a/hw/arm/smmuv3.c >> +++ b/hw/arm/smmuv3.c >> @@ -24,6 +24,7 @@ >>   #include "hw/qdev-properties.h" >>   #include "hw/qdev-core.h" >>   #include "hw/pci/pci.h" >> +#include "hw/pci/pci_bridge.h" >>   #include "cpu.h" >>   #include "exec/target_page.h" >>   #include "trace.h" >> @@ -1874,6 +1875,25 @@ static void smmu_reset_exit(Object *obj, >> ResetType type) >>       smmuv3_init_regs(s); >>   } >>   +static int smmuv3_pcie_bus(Object *obj, void *opaque) >> +{ >> +    DeviceState *d = opaque; >> +    PCIBus *bus; >> + >> +    if (!object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { >> +        return 0; >> +    } >> + >> +    bus = PCI_HOST_BRIDGE(obj)->bus; >> +    if (d->parent_bus && !strcmp(bus->qbus.name, >> d->parent_bus->name)) { >> +        object_property_set_link(OBJECT(d), "primary-bus", OBJECT(bus), >> +                                 &error_abort); >> +        /* Return non-zero as we got the bus and don't need further >> iteration.*/ >> +        return 1; >> +    } >> +    return 0; >> +} >> + >>   static void smmu_realize(DeviceState *d, Error **errp) >>   { >>       SMMUState *sys = ARM_SMMU(d); >> @@ -1882,6 +1902,10 @@ static void smmu_realize(DeviceState *d, Error >> **errp) >>       SysBusDevice *dev = SYS_BUS_DEVICE(d); >>       Error *local_err = NULL; >>   +    if (!object_property_get_link(OBJECT(d), "primary-bus", >> &error_abort)) { >> +        object_child_foreach_recursive(object_get_root(), >> smmuv3_pcie_bus, d); >> +    } >> + >>       c->parent_realize(d, &local_err); >>       if (local_err) { >>           error_propagate(errp, local_err); >> @@ -1996,6 +2020,8 @@ static void smmuv3_class_init(ObjectClass >> *klass, const void *data) >>       device_class_set_parent_realize(dc, smmu_realize, >>                                       &c->parent_realize); >>       device_class_set_props(dc, smmuv3_properties); >> +    dc->hotpluggable = false; >> +    dc->bus_type = TYPE_PCIE_BUS; > Does this force legacy SMMUv3 to be tied to a PCIe bus now? > if so, will that break some existing legacy smmuv3 configs?, i.e., > virtio-scsi attached to a legacy smmuv3. Previously the SMMU was already always attached to a PCI primary-bus (vms->bus ie. pci0). virtio-scsi-pci is the device being protected. The SMMU is not able to protect platforms devices atm. My only concern is we are highjacking the "bus" prop to record the bus hierarchy the SMMU is protecting. While the SMMU is a platform device and does not inherit the PCI device base class its bus type becomes "TYPE_PCIE_BUS". So in terms of qom hierachy is is seen as a PCI device now? I don't know if it is a problem. An alternative could be to keep the bus pointer and type as it was before and introduce a primary-bus property. Adding Markus, Peter, Daniel and Alex in to. At some point it was envisionned to support protected platform devices (I think this was need for CCA). My fear is that if we turn the bus type to PCIE it may be difficult to extend the support to non PCIe protected devices. The SMMU shall remain a platform device being able to protect either PCI devices and, in the future, platform devices. Thanks Eric > >>   } >>     static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, >> diff --git a/hw/arm/virt.c b/hw/arm/virt.c >> index 177f3dd22c..3bae4e374f 100644 >> --- a/hw/arm/virt.c >> +++ b/hw/arm/virt.c >> @@ -56,6 +56,7 @@ >>   #include "qemu/cutils.h" >>   #include "qemu/error-report.h" >>   #include "qemu/module.h" >> +#include "hw/pci/pci_bus.h" >>   #include "hw/pci-host/gpex.h" >>   #include "hw/virtio/virtio-pci.h" >>   #include "hw/core/sysbus-fdt.h" >> @@ -1442,7 +1443,7 @@ static void create_smmu(const VirtMachineState >> *vms, >>       } >>       object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), >>                                &error_abort); >> -    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); >> +    qdev_realize_and_unref(dev, &bus->qbus, &error_fatal); >>       sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); >>       for (i = 0; i < NUM_SMMU_IRQS; i++) { >>           sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, >