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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a099ae7b45sm9586575f8f.46.2025.05.05.02.01.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 May 2025 02:01:55 -0700 (PDT) Message-ID: Date: Mon, 5 May 2025 11:01:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] hw/arm/virt: Factor out common SMMUV3 dt bindings code Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250502102707.110516-1-shameerali.kolothum.thodi@huawei.com> <20250502102707.110516-4-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: <20250502102707.110516-4-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.411, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 5/2/25 12:27 PM, Shameer Kolothum wrote: > No functional changes intended. This will be useful when we > add support for user-creatable smmuv3 device. > > Signed-off-by: Shameer Kolothum > --- > hw/arm/virt.c | 54 +++++++++++++++++++++++++++------------------------ > 1 file changed, 29 insertions(+), 25 deletions(-) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index dd355f4454..464e84ae67 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -1418,19 +1418,43 @@ static void create_pcie_irq_map(const MachineState *ms, > 0x7 /* PCI irq */); > } > > +static void create_smmuv3_dt_bindings(const VirtMachineState *vms, hwaddr base, > + hwaddr size, int irq) > +{ > + char *node; > + const char compat[] = "arm,smmu-v3"; > + const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; > + MachineState *ms = MACHINE(vms); > + > + node = g_strdup_printf("/smmuv3@%" PRIx64, base); > + qemu_fdt_add_subnode(ms->fdt, node); > + qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); > + qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); > + > + qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", > + GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, > + GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, > + GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, > + GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); > + > + qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, > + sizeof(irq_names)); > + > + qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); > + qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); > + qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); > + g_free(node); > +} > + > static void create_smmu(const VirtMachineState *vms, > PCIBus *bus) > { > VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); > - char *node; > - const char compat[] = "arm,smmu-v3"; > int irq = vms->irqmap[VIRT_SMMU]; > int i; > hwaddr base = vms->memmap[VIRT_SMMU].base; > hwaddr size = vms->memmap[VIRT_SMMU].size; > - const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; > DeviceState *dev; > - MachineState *ms = MACHINE(vms); > > if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { > return; > @@ -1449,27 +1473,7 @@ static void create_smmu(const VirtMachineState *vms, > sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, > qdev_get_gpio_in(vms->gic, irq + i)); > } > - > - node = g_strdup_printf("/smmuv3@%" PRIx64, base); > - qemu_fdt_add_subnode(ms->fdt, node); > - qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); > - qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); > - > - qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", > - GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, > - GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, > - GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, > - GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); > - > - qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, > - sizeof(irq_names)); > - > - qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); > - > - qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); > - > - qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); > - g_free(node); > + create_smmuv3_dt_bindings(vms, base, size, irq); > } > > static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) Reviewed-by: Eric Auger nothing to do with that patch but I just noticed we omitted to support the bypass_iommu=true along with DT mode. I don't see the iommu-map property set accordingly. Something to further consolidate? Eric Eric