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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429c1142e7dsm21585579f8f.17.2025.11.03.09.16.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Nov 2025 09:16:43 -0800 (PST) Message-ID: Date: Mon, 3 Nov 2025 18:16:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 19/32] hw/arm/smmuv3-accel: Get host SMMUv3 hw info and validate Content-Language: en-US To: Shameer Kolothum , Zhangfei Gao Cc: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , Jason Gunthorpe , Nicolin Chen , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , Krishnakant Jaju References: <20251031105005.24618-1-skolothumtho@nvidia.com> <20251031105005.24618-20-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/3/25 4:42 PM, Shameer Kolothum wrote: > >> -----Original Message----- >> From: Zhangfei Gao >> Sent: 01 November 2025 14:20 >> To: Shameer Kolothum >> Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org; >> eric.auger@redhat.com; peter.maydell@linaro.org; Jason Gunthorpe >> ; Nicolin Chen ; >> ddutile@redhat.com; berrange@redhat.com; Nathan Chen >> ; Matt Ochs ; >> smostafa@google.com; wangzhou1@hisilicon.com; >> jiangkunkun@huawei.com; jonathan.cameron@huawei.com; >> zhenzhong.duan@intel.com; yi.l.liu@intel.com; Krishnakant Jaju >> >> Subject: Re: [PATCH v5 19/32] hw/arm/smmuv3-accel: Get host SMMUv3 hw >> info and validate >> >> External email: Use caution opening links or attachments >> >> >> Hi, Shameer >> >> On Fri, 31 Oct 2025 at 18:54, Shameer Kolothum >> wrote: >>> Just before the device gets attached to the SMMUv3, make sure QEMU >>> SMMUv3 features are compatible with the host SMMUv3. >>> >>> Not all fields in the host SMMUv3 IDR registers are meaningful for >> userspace. >>> Only the following fields can be used: >>> >>> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, >> TTF >>> - IDR1: SIDSIZE, SSIDSIZE >>> - IDR3: BBML, RIL >>> - IDR5: VAX, GRAN64K, GRAN16K, GRAN4K >>> >>> For now, the check is to make sure the features are in sync to enable >>> basic accelerated SMMUv3 support. >>> >>> Signed-off-by: Shameer Kolothum >>> --- >>> hw/arm/smmuv3-accel.c | 100 >>> ++++++++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 100 insertions(+) >>> >>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index >>> a2deda3c32..8b9f88dd8e 100644 >>> --- a/hw/arm/smmuv3-accel.c >>> +++ b/hw/arm/smmuv3-accel.c >>> @@ -28,6 +28,98 @@ MemoryRegion root; >>> MemoryRegion sysmem; >>> static AddressSpace *shared_as_sysmem; >>> >>> +static bool >>> +smmuv3_accel_check_hw_compatible(SMMUv3State *s, >>> + struct iommu_hw_info_arm_smmuv3 *info, >>> + Error **errp) { >>> + /* QEMU SMMUv3 supports architecture version 3.1 */ >>> + if (info->aidr < s->aidr) { >>> + error_setg(errp, "Host SMMUv3 architecture version not compatible"); >>> + return false; >>> + } >> Why has this requirement? > Right. That was added based on a comment from Eric here, > https://lore.kernel.org/all/b6105534-4a17-4700-bb0b-e961babd10bb@redhat.com/ > >> We have SMMUv3 version 3.0 and info->aidr = 0. >> and qemu fails to boot here. > Hmm.. It is true that there are hardware out there which implements a cross > section of features from architecture revisions. > > Since we are checking the ID registers that matters here individually anyway, > I am not sure whether we should restrict those with AIDR mismatch or just > warn the user. OK. Just maybe document its is irrelevant to check AIDR in the commit msg for that reason. With that commit msg update + removal of AIDR code feel free to take my Reviewed-by: Eric Auger Eric > > Thanks, > Shameer > > >