From: Richard Henderson <richard.henderson@linaro.org>
To: Alex Zuepke <alex.zuepke@tum.de>
Cc: "open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH] target/arm: read access to performance counters from EL0
Date: Wed, 4 May 2022 10:36:37 -0500 [thread overview]
Message-ID: <fda18484-f36c-0646-2df1-0831e9a60dec@linaro.org> (raw)
In-Reply-To: <20220428132717.84190-1-alex.zuepke@tum.de>
On 4/28/22 06:27, Alex Zuepke wrote:
> The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
> to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
> we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.
>
> Signed-off-by: Alex Zuepke<alex.zuepke@tum.de>
> ---
> target/arm/helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2022-05-04 16:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-28 13:27 [PATCH] target/arm: read access to performance counters from EL0 Alex Zuepke
2022-05-04 8:20 ` Alex Zuepke
2022-05-04 12:48 ` Peter Maydell
2022-05-04 15:36 ` Richard Henderson [this message]
2022-05-05 8:36 ` Peter Maydell
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