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([2602:47:d49d:ec01:ecdc:4f14:189e:85b3]) by smtp.gmail.com with ESMTPSA id g3-20020a1709026b4300b0016eef326febsm8068964plt.1.2022.08.29.15.54.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Aug 2022 15:54:06 -0700 (PDT) Message-ID: Date: Mon, 29 Aug 2022 15:54:04 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 1/1] target/i386: Raise #GP on unaligned m128 accesses when required. Content-Language: en-US To: Ricky Zhou Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20220829142326.39562-1-ricky@rzhou.org> <20220829142326.39562-2-ricky@rzhou.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/29/22 13:46, Ricky Zhou wrote: > Thanks for taking a look at this - did you see the bit in the cover > letter where I discuss doing this via alignment requirements on the > memory operation? My logic was that the memop alignment checks seem to > be more oriented towards triggering #AC exceptions (even though this is > not currently implemented), I missed that in the cover. However... implementing #AC is pretty hypothetical. It's not something that I've ever seen used, and not something that anyone has asked for. > One slightly more involved way to use alignment on the MemOp could be to > arrange to pass the problematic MemOp to do_unaligned_access and > helper_unaligned_{ld,st}. Then we could allow CPUs to handle > misalignment of different MemOps differently (e.g. raise #GP/SIGSEGV for > certain ops and #AC/SIGBUS for others). For this change to x86, we could > maybe get away with making MO_ALIGN_16 and above trigger #GP/SIGSEGV and > everything else trigger #AC/SIGBUS. If that's a little hacky, we could > instead add some dedicated bits to MemOp that distinguish different > types of unaligned accesses. There's another related problem that actually has gotten a bug report in the past: when the form of the address should raise #SS instead of #GP in system mode. My initial thought was to record information about "the" memory access in the per-insn unwind info, until I realized that there are insns with multiple memory operations requiring different treatment. E.g. "push (%rax)", where the read might raise #GP and the write might raise #SS. So I think we'd need to encode #GP vs #SS into the mmu_idx used (e.g. in the lsb). However, I don't think there are any similar situations of multiple memory types affecting SSE, so #AC vs #GP could in fact be encoded into the per-insn unwind info. As for SIGBUS vs SIGSEGV for SSE and user-only, you only need implement the x86_cpu_ops.record_sigbus hook. C.f. the s390x version which raises PGM_SPECIFICATION -> SIGILL for unaligned atomic operations. r~