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Wed, 02 Jul 2025 07:48:24 -0700 (PDT) Received: from [192.168.68.110] ([189.110.107.157]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b34e300468esm13343868a12.7.2025.07.02.07.48.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Jul 2025 07:48:23 -0700 (PDT) Message-ID: Date: Wed, 2 Jul 2025 11:48:18 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv: rvv: Minimum VLEN needs to respect V/Zve extensions To: Max Chou , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei References: <20250627132156.440214-1-max.chou@sifive.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250627132156.440214-1-max.chou@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/27/25 10:21 AM, Max Chou wrote: > According to the RISC-V instruction set manual, the minimum VLEN needs > to respect the following extensions: > > Extension Minimum VLEN > * V 128 > * Zve64[d|f|x] 64 > * Zve32[f|x] 32 > > Signed-off-by: Max Chou > --- > target/riscv/tcg/tcg-cpu.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 163e7ce3642..187534009dd 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -416,12 +416,21 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) > static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > Error **errp) > { > + uint32_t min_vlen; > uint32_t vlen = cfg->vlenb << 3; > > - if (vlen > RV_VLEN_MAX || vlen < 128) { > + if (riscv_has_ext(env, RVV)) { > + min_vlen = 128; > + } else if (cfg->ext_zve64x) { > + min_vlen = 64; > + } else if (cfg->ext_zve32x) { > + min_vlen = 32; > + } At this moment this is how we're calling riscv_cpu_validate_v(): if (riscv_has_ext(env, RVV)) { riscv_cpu_validate_v(env, &cpu->cfg, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } } riscv_has_ext(env, RVV) is always true inside the function. The code above will always result in min_vlen = 128 because of the 'else if' chaining. IIUC the idea of the patch, what you want is something like: > + uint32_t min_vlen = 128; > uint32_t vlen = cfg->vlenb << 3; > > - if (vlen > RV_VLEN_MAX || vlen < 128) { > + if (cfg->ext_zve64x) { > + min_vlen = 64; > + } else if (cfg->ext_zve32x) { > + min_vlen = 32; > + } I.e. init min_vlen to 128 (since RVV is always true) and then change it according to zve64x and zve32x. Thanks, Daniel > + > + if (vlen > RV_VLEN_MAX || vlen < min_vlen) { > error_setg(errp, > "Vector extension implementation only supports VLEN " > - "in the range [128, %d]", RV_VLEN_MAX); > + "in the range [%d, %d]", min_vlen, RV_VLEN_MAX); > return; > } >