Re: [Qemu-devel] [PATCH v4 08/13] tcg: Add opcodes for vector vmrgh instructions

[Richard Henderson <richard.henderson@linaro.org>]

On 6/27/19 12:56 PM, Stefan Brankovic wrote:
> +void tcg_gen_gvec_vmrgh(unsigned vece, uint32_t dofs, uint32_t aofs,
> +                       uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
> +{
> +    static const GVecGen3 g[3] = {
> +        { .fniv = tcg_gen_vmrgh_vec,
> +          .fno = gen_helper_gvec_vmrgh8,
> +          .opt_opc = vecop_list_vmrgh,
> +          .vece = MO_8 },
> +        { .fniv = tcg_gen_vmrgh_vec,
> +          .fno = gen_helper_gvec_vmrgh16,
> +          .opt_opc = vecop_list_vmrgh,
> +          .vece = MO_16 },
> +        { .fniv = tcg_gen_vmrgh_vec,
> +          .fno = gen_helper_gvec_vmrgh32,
> +          .opt_opc = vecop_list_vmrgh,
> +          .vece = MO_32 }
> +    };
> +    tcg_debug_assert(vece <= MO_64);
> +    tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);

By the by, you've missed out on the 64-bit operation, which your assert allows
(and should be available, if this is supposed to be a generic operation).

Also, because this operation does not move data in strict columns between the
input and output vectors, you can't use tcg_gen_gvec_3.  You'd need to write
custom code in order to allow 2 VEC128 to implement the merge for a VEC256 (or
any other combination allowed by MAXSZ).


r~