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[37.158.132.66]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47787e43c2fsm298845525e9.6.2025.11.17.07.14.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Nov 2025 07:14:43 -0800 (PST) Message-ID: Date: Mon, 17 Nov 2025 16:14:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v2 03/10] target/arm: add TCSO bitmasks to SCTLR To: Gabriel Brookman , qemu-devel@nongnu.org Cc: Peter Maydell , Gustavo Romero , qemu-arm@nongnu.org References: <20251116-feat-mte4-v2-0-9a7122b7fa76@gmail.com> <20251116-feat-mte4-v2-3-9a7122b7fa76@gmail.com> From: Richard Henderson Content-Language: en-US In-Reply-To: <20251116-feat-mte4-v2-3-9a7122b7fa76@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/17/25 02:40, Gabriel Brookman wrote: > These are the bitmasks used to control the FEAT_MTE_STORE_ONLY feature. > They are now named and setting these fields of SCTLR is ignored if MTE > is disabled, as per convention. > > Signed-off-by: Gabriel Brookman > --- > target/arm/cpu.h | 2 ++ > target/arm/helper.c | 4 ++-- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 39f2b2e54d..6fe85b5e3a 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1424,6 +1424,8 @@ void pmu_init(ARMCPU *cpu); > #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ > #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ > #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ > +#define SCTLR_TCSO0 (1ULL << 58) /* FEAT_MTE_STORE_ONLY */ > +#define SCTLR_TCSO (1ULL << 59) /* FEAT_MTE_STORE_ONLY */ > #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ Indentation is off. > @@ -3364,10 +3364,10 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, > > if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { > if (ri->opc1 == 6) { /* SCTLR_EL3 */ > - value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); > + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA | SCTLR_TCSO); > } else { > value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | > - SCTLR_ATA0 | SCTLR_ATA); > + SCTLR_ATA0 | SCTLR_ATA | SCTLR_TCSO | SCTLR_TCSO0); > } > } You should be testing for FEAT_MTE_STORE_ONLY, not just plain MTE (since renamed MTE2). Add the appropriate function to cpu-features.h. r~