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([2400:4050:a840:1e00:78d2:b862:10a7:d486]) by smtp.gmail.com with ESMTPSA id m9-20020a170902c44900b001ba066c589dsm3384708plm.137.2023.10.18.05.19.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Oct 2023 05:19:17 -0700 (PDT) Message-ID: Date: Wed, 18 Oct 2023 21:19:13 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] target/riscv: Remove misa_mxl validation To: LIU Zhiwei Cc: =?UTF-8?Q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , qemu-devel@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , "open list:RISC-V TCG CPUs" , Richard Henderson References: <20231012054223.37870-1-akihiko.odaki@daynix.com> <20231012054223.37870-2-akihiko.odaki@daynix.com> <5147b65f-8211-4355-b667-f450dc189ae3@linux.alibaba.com> <64c66917-2e17-47f6-ad0e-a90d7d89eec1@daynix.com> Content-Language: en-US From: Akihiko Odaki In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=2607:f8b0:4864:20::42b; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2023/10/18 14:53, LIU Zhiwei wrote: > +CC Richard > > On 2023/10/17 11:37, Akihiko Odaki wrote: >> On 2023/10/17 11:29, LIU Zhiwei wrote: >>> >>> On 2023/10/12 13:42, Akihiko Odaki wrote: >>>> It is initialized with a simple assignment and there is little room for >>>> error. In fact, the validation is even more complex. >>>> >>>> Signed-off-by: Akihiko Odaki >>>> --- >>>>   target/riscv/cpu.c | 13 ++----------- >>>>   1 file changed, 2 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >>>> index f5572704de..550b357fb7 100644 >>>> --- a/target/riscv/cpu.c >>>> +++ b/target/riscv/cpu.c >>>> @@ -1042,7 +1042,7 @@ static void >>>> riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) >>>>       } >>>>   } >>>> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) >>>> +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) >>>>   { >>>>       RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); >>>>       CPUClass *cc = CPU_CLASS(mcc); >>>> @@ -1062,11 +1062,6 @@ static void >>>> riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) >>>>       default: >>>>           g_assert_not_reached(); >>>>       } >>>> - >>>> -    if (env->misa_mxl_max != env->misa_mxl) { >>>> -        error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); >>>> -        return; >>>> -    } >>>>   } >>>>   /* >>>> @@ -1447,11 +1442,7 @@ static void riscv_cpu_realize_tcg(DeviceState >>>> *dev, Error **errp) >>>>           return; >>>>       } >>>> -    riscv_cpu_validate_misa_mxl(cpu, &local_err); >>>> -    if (local_err != NULL) { >>>> -        error_propagate(errp, local_err); >>>> -        return; >>>> -    } >>>> +    riscv_cpu_validate_misa_mxl(cpu); >>> >>> This it not right.  As we are still working on the supporting for >>> MXL32 or SXL32, this validation is needed. >> >> It's not preventing supporting MXL32 or SXL32. It's removing >> env->misa_mxl_max != env->misa_mxl just because it's initialized with >> a simple statement: >> env->misa_mxl_max = env->misa_mxl = mxl; >> >> It makes little sense to have a validation code that is more complex >> than the validated code. >> >>> >>> And we can't ensure the all RISC-V cpus have the same misa_mxl_max or >>> misa_mxl,   it is not right to move it to class. >>> For example, in the future, riscv64-softmmu can run 32-bit cpu and >>> 64-bit cpu. And maybe in heterogeneous SOC, >>> we have 32-bit cpu and 64-bit cpu together. >> >> This patch series does not touch misa_mxl. We don't need to ensure >> that all CPUs have the same misa_mxl_max, but we just need to ensure >> that CPUs in the same class do. Creating a heterogeneous SoC is still >> possible by combining e.g. TYPE_RISCV_CPU_SIFIVE_E31 and >> TYPE_RISCV_CPU_SIFIVE_E51, for example. > > I see what you mean. It makes sense  to move the misa_mxl_max field from > env to the class struct. The misa_mxl_max  is always be set by  cpu init > or the migration. > > The former  is OK. I don't know whether QEMU supports migration from > 32-bit CPU to 64-bit CPU. Otherwise, > > Acked-by: LIU Zhiwei It doesn't. docs/devel/migration.rst states: > For this to work, QEMU has to be launched with the same arguments the > two times. I.e. it can only restore the state in one guest that has > the same devices that the one it was saved (this last requirement can > be relaxed a bit, but for now we can consider that configuration has > to be exactly the same). The corresponding CPUs in two QEMU instances launched with the same arguments will have the same misa_mxl_max values.