* [PULL 00/48] virtio,pc,pci: features, fixes, cleanups
@ 2025-01-15 18:08 Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature Michael S. Tsirkin
` (50 more replies)
0 siblings, 51 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging (2025-01-14 12:46:56 -0500)
are available in the Git repository at:
https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
for you to fetch changes up to 60f543ad917fad731e39ff8ce2ca83b9a9cc9d90:
virtio-net: vhost-user: Implement internal migration (2025-01-15 13:07:34 -0500)
----------------------------------------------------------------
virtio,pc,pci: features, fixes, cleanups
The big thing here are:
stage-1 translation in vtd
internal migration in vhost-user
ghes driver preparation for error injection
new resource uuid feature in virtio gpu
And as usual, fixes and cleanups.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
----------------------------------------------------------------
Clément Mathieu--Drif (4):
intel_iommu: Check if the input address is canonical
intel_iommu: Set accessed and dirty bits during stage-1 translation
intel_iommu: Add an internal API to find an address space with PASID
intel_iommu: Add support for PASID-based device IOTLB invalidation
Dorinda Bassey (1):
virtio-gpu: Add definition for resource_uuid feature
Igor Mammedov (6):
tests: acpi: whitelist expected blobs
cpuhp: make sure that remove events are handled within the same SCI
tests: acpi: update expected blobs
tests: acpi: whitelist expected blobs
pci: acpi: Windows 'PCI Label Id' bug workaround
tests: acpi: update expected blobs
Laurent Vivier (2):
vhost: Add stubs for the migration state transfer interface
virtio-net: vhost-user: Implement internal migration
Li Zhijian (1):
hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`
Mauro Carvalho Chehab (16):
acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED
acpi/ghes: simplify acpi_ghes_record_errors() code
acpi/ghes: simplify the per-arch caller to build HEST table
acpi/ghes: better handle source_id and notification
acpi/ghes: Fix acpi_ghes_record_errors() argument
acpi/ghes: Remove a duplicated out of bounds check
acpi/ghes: Change the type for source_id
acpi/ghes: don't check if physical_address is not zero
acpi/ghes: make the GHES record generation more generic
acpi/ghes: better name GHES memory error function
acpi/ghes: don't crash QEMU if ghes GED is not found
acpi/ghes: rename etc/hardware_error file macros
acpi/ghes: better name the offset of the hardware error firmware
acpi/ghes: move offset calculus to a separate function
acpi/ghes: Change ghes fill logic to work with only one source
docs: acpi_hest_ghes: fix documentation for CPER size
Nicholas Piggin (1):
pci/msix: Fix msix pba read vector poll end calculation
Sebastian Ott (1):
pci: ensure valid link status bits for downstream ports
Yi Liu (2):
intel_iommu: Rename slpte to pte
intel_iommu: Implement stage-1 translation
Yu Zhang (1):
intel_iommu: Use the latest fault reasons defined by spec
Zhenzhong Duan (13):
intel_iommu: Make pasid entry type check accurate
intel_iommu: Add a placeholder variable for scalable mode stage-1 translation
intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation
intel_iommu: Check stage-1 translation result with interrupt range
intel_iommu: Flush stage-1 cache in iotlb invalidation
intel_iommu: Process PASID-based iotlb invalidation
intel_iommu: piotlb invalidation should notify unmap
tests/acpi: q35: allow DMAR acpi table changes
intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2
tests/acpi: q35: Update host address width in DMAR
intel_iommu: Introduce a property x-flts for stage-1 translation
intel_iommu: Introduce a property to control FS1GP cap bit setting
tests/qtest: Add intel-iommu test
hw/i386/intel_iommu_internal.h | 101 ++-
include/hw/acpi/ghes.h | 16 +-
include/hw/i386/intel_iommu.h | 8 +-
include/hw/virtio/vhost.h | 23 +
include/hw/virtio/virtio-gpu.h | 3 +
hw/acpi/cpu.c | 43 +-
hw/acpi/generic_event_device.c | 4 +-
hw/acpi/ghes-stub.c | 2 +-
hw/acpi/ghes.c | 256 ++++----
hw/arm/virt-acpi-build.c | 5 +-
hw/display/vhost-user-gpu.c | 8 +
hw/display/virtio-gpu-base.c | 3 +
hw/i386/acpi-build.c | 33 +-
hw/i386/intel_iommu.c | 734 +++++++++++++++++-----
hw/i386/pc.c | 1 +
hw/mem/cxl_type3.c | 2 +-
hw/net/virtio-net.c | 135 +++-
hw/pci/msix.c | 2 +-
hw/pci/pcie.c | 12 +-
target/arm/kvm.c | 2 +-
tests/qtest/intel-iommu-test.c | 64 ++
MAINTAINERS | 1 +
docs/specs/acpi_hest_ghes.rst | 6 +-
tests/data/acpi/x86/pc/DSDT | Bin 8526 -> 8611 bytes
tests/data/acpi/x86/pc/DSDT.acpierst | Bin 8437 -> 8522 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat | Bin 9851 -> 9936 bytes
tests/data/acpi/x86/pc/DSDT.bridge | Bin 15397 -> 15482 bytes
tests/data/acpi/x86/pc/DSDT.cphp | Bin 8990 -> 9075 bytes
tests/data/acpi/x86/pc/DSDT.dimmpxm | Bin 10180 -> 10265 bytes
tests/data/acpi/x86/pc/DSDT.hpbridge | Bin 8477 -> 8562 bytes
tests/data/acpi/x86/pc/DSDT.hpbrroot | Bin 5033 -> 5100 bytes
tests/data/acpi/x86/pc/DSDT.ipmikcs | Bin 8598 -> 8683 bytes
tests/data/acpi/x86/pc/DSDT.memhp | Bin 9885 -> 9970 bytes
tests/data/acpi/x86/pc/DSDT.nohpet | Bin 8384 -> 8469 bytes
tests/data/acpi/x86/pc/DSDT.numamem | Bin 8532 -> 8617 bytes
tests/data/acpi/x86/pc/DSDT.roothp | Bin 12319 -> 12404 bytes
tests/data/acpi/x86/q35/DMAR.dmar | Bin 120 -> 120 bytes
tests/data/acpi/x86/q35/DSDT | Bin 8355 -> 8440 bytes
tests/data/acpi/x86/q35/DSDT.acpierst | Bin 8372 -> 8457 bytes
tests/data/acpi/x86/q35/DSDT.acpihmat | Bin 9680 -> 9765 bytes
tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x | Bin 12565 -> 12650 bytes
tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator | Bin 8634 -> 8719 bytes
tests/data/acpi/x86/q35/DSDT.applesmc | Bin 8401 -> 8486 bytes
tests/data/acpi/x86/q35/DSDT.bridge | Bin 11968 -> 12053 bytes
tests/data/acpi/x86/q35/DSDT.core-count | Bin 12913 -> 12998 bytes
tests/data/acpi/x86/q35/DSDT.core-count2 | Bin 33770 -> 33855 bytes
tests/data/acpi/x86/q35/DSDT.cphp | Bin 8819 -> 8904 bytes
tests/data/acpi/x86/q35/DSDT.cxl | Bin 13146 -> 13231 bytes
tests/data/acpi/x86/q35/DSDT.dimmpxm | Bin 10009 -> 10094 bytes
tests/data/acpi/x86/q35/DSDT.ipmibt | Bin 8430 -> 8515 bytes
tests/data/acpi/x86/q35/DSDT.ipmismbus | Bin 8443 -> 8528 bytes
tests/data/acpi/x86/q35/DSDT.ivrs | Bin 8372 -> 8457 bytes
tests/data/acpi/x86/q35/DSDT.memhp | Bin 9714 -> 9799 bytes
tests/data/acpi/x86/q35/DSDT.mmio64 | Bin 9485 -> 9570 bytes
tests/data/acpi/x86/q35/DSDT.multi-bridge | Bin 13208 -> 13293 bytes
tests/data/acpi/x86/q35/DSDT.noacpihp | Bin 8235 -> 8302 bytes
tests/data/acpi/x86/q35/DSDT.nohpet | Bin 8213 -> 8298 bytes
tests/data/acpi/x86/q35/DSDT.numamem | Bin 8361 -> 8446 bytes
tests/data/acpi/x86/q35/DSDT.pvpanic-isa | Bin 8456 -> 8541 bytes
tests/data/acpi/x86/q35/DSDT.thread-count | Bin 12913 -> 12998 bytes
tests/data/acpi/x86/q35/DSDT.thread-count2 | Bin 33770 -> 33855 bytes
tests/data/acpi/x86/q35/DSDT.tis.tpm12 | Bin 8961 -> 9046 bytes
tests/data/acpi/x86/q35/DSDT.tis.tpm2 | Bin 8987 -> 9072 bytes
tests/data/acpi/x86/q35/DSDT.type4-count | Bin 18589 -> 18674 bytes
tests/data/acpi/x86/q35/DSDT.viot | Bin 14612 -> 14697 bytes
tests/data/acpi/x86/q35/DSDT.xapic | Bin 35718 -> 35803 bytes
tests/qtest/meson.build | 1 +
67 files changed, 1132 insertions(+), 333 deletions(-)
create mode 100644 tests/qtest/intel-iommu-test.c
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 02/48] pci: ensure valid link status bits for downstream ports Michael S. Tsirkin
` (49 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Dorinda Bassey, Stefano Garzarella,
Marc-André Lureau
From: Dorinda Bassey <dbassey@redhat.com>
Add the VIRTIO_GPU_F_RESOURCE_UUID feature to enable the assignment
of resources UUIDs for export to other virtio devices.
Signed-off-by: Dorinda Bassey <dbassey@redhat.com>
Message-Id: <20241007070013.3350752-1-dbassey@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/virtio/virtio-gpu.h | 3 +++
hw/display/vhost-user-gpu.c | 8 ++++++++
hw/display/virtio-gpu-base.c | 3 +++
3 files changed, 14 insertions(+)
diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h
index bd93672185..a42957c4e2 100644
--- a/include/hw/virtio/virtio-gpu.h
+++ b/include/hw/virtio/virtio-gpu.h
@@ -98,6 +98,7 @@ enum virtio_gpu_base_conf_flags {
VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED,
VIRTIO_GPU_FLAG_RUTABAGA_ENABLED,
VIRTIO_GPU_FLAG_VENUS_ENABLED,
+ VIRTIO_GPU_FLAG_RESOURCE_UUID_ENABLED,
};
#define virtio_gpu_virgl_enabled(_cfg) \
@@ -114,6 +115,8 @@ enum virtio_gpu_base_conf_flags {
(_cfg.flags & (1 << VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED))
#define virtio_gpu_rutabaga_enabled(_cfg) \
(_cfg.flags & (1 << VIRTIO_GPU_FLAG_RUTABAGA_ENABLED))
+#define virtio_gpu_resource_uuid_enabled(_cfg) \
+ (_cfg.flags & (1 << VIRTIO_GPU_FLAG_RESOURCE_UUID_ENABLED))
#define virtio_gpu_hostmem_enabled(_cfg) \
(_cfg.hostmem > 0)
#define virtio_gpu_venus_enabled(_cfg) \
diff --git a/hw/display/vhost-user-gpu.c b/hw/display/vhost-user-gpu.c
index 12d5c37ee5..2aed6243f6 100644
--- a/hw/display/vhost-user-gpu.c
+++ b/hw/display/vhost-user-gpu.c
@@ -631,6 +631,14 @@ vhost_user_gpu_device_realize(DeviceState *qdev, Error **errp)
error_report("EDID requested but the backend doesn't support it.");
g->parent_obj.conf.flags &= ~(1 << VIRTIO_GPU_FLAG_EDID_ENABLED);
}
+ if (virtio_has_feature(g->vhost->dev.features,
+ VIRTIO_GPU_F_RESOURCE_UUID)) {
+ g->parent_obj.conf.flags |= 1 << VIRTIO_GPU_FLAG_RESOURCE_UUID_ENABLED;
+ }
+ if (virtio_has_feature(g->vhost->dev.features,
+ VIRTIO_GPU_F_RESOURCE_UUID)) {
+ g->parent_obj.conf.flags |= 1 << VIRTIO_GPU_FLAG_RESOURCE_UUID_ENABLED;
+ }
if (!virtio_gpu_base_device_realize(qdev, NULL, NULL, errp)) {
return;
diff --git a/hw/display/virtio-gpu-base.c b/hw/display/virtio-gpu-base.c
index 4fc7ef8896..7827536ac4 100644
--- a/hw/display/virtio-gpu-base.c
+++ b/hw/display/virtio-gpu-base.c
@@ -235,6 +235,9 @@ virtio_gpu_base_get_features(VirtIODevice *vdev, uint64_t features,
if (virtio_gpu_context_init_enabled(g->conf)) {
features |= (1 << VIRTIO_GPU_F_CONTEXT_INIT);
}
+ if (virtio_gpu_resource_uuid_enabled(g->conf)) {
+ features |= (1 << VIRTIO_GPU_F_RESOURCE_UUID);
+ }
return features;
}
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 02/48] pci: ensure valid link status bits for downstream ports
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 03/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
` (48 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sebastian Ott, Zhenyu Zhang, Alex Williamson,
Marcel Apfelbaum
From: Sebastian Ott <sebott@redhat.com>
PCI hotplug for downstream endpoints on arm fails because Linux'
PCIe hotplug driver doesn't like the QEMU provided LNKSTA:
pcieport 0000:08:01.0: pciehp: Slot(2): Card present
pcieport 0000:08:01.0: pciehp: Slot(2): Link Up
pcieport 0000:08:01.0: pciehp: Slot(2): Cannot train link: status 0x2000
There's 2 cases where LNKSTA isn't setup properly:
* the downstream device has no express capability
* max link width of the bridge is 0
Move the sanity checks added via 88c869198aa63
("pci: Sanity test minimum downstream LNKSTA") outside of the
branch to make sure downstream ports always have a valid LNKSTA.
Signed-off-by: Sebastian Ott <sebott@redhat.com>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-Id: <20241203121928.14861-1-sebott@redhat.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/pci/pcie.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 0b455c8654..1b12db6fa2 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -1113,18 +1113,22 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev)
if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) {
lnksta &= ~PCI_EXP_LNKSTA_NLW;
lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW;
- } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) {
- lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1);
}
if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) {
lnksta &= ~PCI_EXP_LNKSTA_CLS;
lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS;
- } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) {
- lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT);
}
}
+ if (!(lnksta & PCI_EXP_LNKSTA_NLW)) {
+ lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1);
+ }
+
+ if (!(lnksta & PCI_EXP_LNKSTA_CLS)) {
+ lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT);
+ }
+
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta &
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 03/48] tests: acpi: whitelist expected blobs
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 02/48] pci: ensure valid link status bits for downstream ports Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI Michael S. Tsirkin
` (47 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Igor Mammedov, Eric Mackay, Ani Sinha
From: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20241210163945.3422623-2-imammedo@redhat.com>
Tested-by: Eric Mackay <eric.mackay@oracle.com>
Acked-by: Ani Sinha <anisinha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 42 +++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..a1047913af 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,43 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/x86/pc/DSDT",
+"tests/data/acpi/x86/pc/DSDT.acpierst",
+"tests/data/acpi/x86/pc/DSDT.acpihmat",
+"tests/data/acpi/x86/pc/DSDT.bridge",
+"tests/data/acpi/x86/pc/DSDT.cphp",
+"tests/data/acpi/x86/pc/DSDT.dimmpxm",
+"tests/data/acpi/x86/pc/DSDT.hpbridge",
+"tests/data/acpi/x86/pc/DSDT.hpbrroot",
+"tests/data/acpi/x86/pc/DSDT.ipmikcs",
+"tests/data/acpi/x86/pc/DSDT.memhp",
+"tests/data/acpi/x86/pc/DSDT.nohpet",
+"tests/data/acpi/x86/pc/DSDT.numamem",
+"tests/data/acpi/x86/pc/DSDT.roothp",
+"tests/data/acpi/x86/q35/DSDT",
+"tests/data/acpi/x86/q35/DSDT.acpierst",
+"tests/data/acpi/x86/q35/DSDT.acpihmat",
+"tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x",
+"tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator",
+"tests/data/acpi/x86/q35/DSDT.applesmc",
+"tests/data/acpi/x86/q35/DSDT.bridge",
+"tests/data/acpi/x86/q35/DSDT.core-count",
+"tests/data/acpi/x86/q35/DSDT.core-count2",
+"tests/data/acpi/x86/q35/DSDT.cphp",
+"tests/data/acpi/x86/q35/DSDT.cxl",
+"tests/data/acpi/x86/q35/DSDT.dimmpxm",
+"tests/data/acpi/x86/q35/DSDT.ipmibt",
+"tests/data/acpi/x86/q35/DSDT.ipmismbus",
+"tests/data/acpi/x86/q35/DSDT.ivrs",
+"tests/data/acpi/x86/q35/DSDT.memhp",
+"tests/data/acpi/x86/q35/DSDT.mmio64",
+"tests/data/acpi/x86/q35/DSDT.multi-bridge",
+"tests/data/acpi/x86/q35/DSDT.noacpihp",
+"tests/data/acpi/x86/q35/DSDT.nohpet",
+"tests/data/acpi/x86/q35/DSDT.numamem",
+"tests/data/acpi/x86/q35/DSDT.pvpanic-isa",
+"tests/data/acpi/x86/q35/DSDT.thread-count",
+"tests/data/acpi/x86/q35/DSDT.thread-count2",
+"tests/data/acpi/x86/q35/DSDT.tis.tpm12",
+"tests/data/acpi/x86/q35/DSDT.tis.tpm2",
+"tests/data/acpi/x86/q35/DSDT.type4-count",
+"tests/data/acpi/x86/q35/DSDT.viot",
+"tests/data/acpi/x86/q35/DSDT.xapic",
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (2 preceding siblings ...)
2025-01-15 18:08 ` [PULL 03/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 05/48] tests: acpi: update expected blobs Michael S. Tsirkin
` (46 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Igor Mammedov, Eric Mackay, Ani Sinha
From: Igor Mammedov <imammedo@redhat.com>
CPU_SCAN_METHOD was processing insert events first and only if insert event was
not present then it would check remove event.
Normally it's not an issue as it doesn't make much sense tho hotplug and
immediately unplug it. In this corner case, which can be reproduced with:
qemu -smp 1,maxcpus=2 -cpu host -monitor stdio \
-drive if=pflash,format=raw,readonly,file=edk2-x86_64-code.fd
* boot till GRUB prompt and pause guest (either via monitor or stop GRUB
from automatic boot)
* at monitor prompt add CPU:
device_add host-x86_64-cpu,socket-id=0,core-id=1,thread-id=0,id=foo
* let guest OS boot completely, and unplug CPU from monitor prompt:
device_del foo
which triggers GPE event that leads to CPU_SCAN_METHOD on guest side
as result of above cpu 'foo' will not be hotunplugged, since QEMU sees
insert event and ignores remove event (leaving it in pending state) for
the GPE event.
Any follow up CPU hotplug/unplug action from QEMU side will handle
previously ignored event, so as workaround user can repeat device_del.
Fix this corner-case by queuing remove events independently from insert
events, aka the same way as we do with insert events. And then go over remove
queue to send eject notify events to OSPM within the same GPE event.
PS:
Process remove queue after the cpu add queue has been processed 1st
to ensure that OSPM gets hotadd evets after hotremove ones.
PS2:
Case where it's still borken happens when guest OS is Linux and
device_del happens before guest OS initializes ACPI subsystem.
Culprit in this case though is the guest kernel, which mangles GPE.sts
(by clearing them up) and thus pending SCI turns to NOP leaving
insert/remove events in pending state.
That is the guest bug and should be fixed there.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reported-by: Eric Mackay <eric.mackay@oracle.com>
Message-Id: <20241210163945.3422623-3-imammedo@redhat.com>
Tested-by: Eric Mackay <eric.mackay@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/cpu.c | 43 ++++++++++++++++++++++++++++++++++---------
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index 9d530a24da..f70a2c045e 100644
--- a/hw/acpi/cpu.c
+++ b/hw/acpi/cpu.c
@@ -327,6 +327,7 @@ const VMStateDescription vmstate_cpu_hotplug = {
#define CPU_EJECT_METHOD "CEJ0"
#define CPU_OST_METHOD "COST"
#define CPU_ADDED_LIST "CNEW"
+#define CPU_EJ_LIST "CEJL"
#define CPU_ENABLED "CPEN"
#define CPU_SELECTOR "CSEL"
@@ -488,7 +489,6 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
method = aml_method(CPU_SCAN_METHOD, 0, AML_SERIALIZED);
{
const uint8_t max_cpus_per_pass = 255;
- Aml *else_ctx;
Aml *while_ctx, *while_ctx2;
Aml *has_event = aml_local(0);
Aml *dev_chk = aml_int(1);
@@ -499,6 +499,8 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
Aml *uid = aml_local(3);
Aml *has_job = aml_local(4);
Aml *new_cpus = aml_name(CPU_ADDED_LIST);
+ Aml *ej_cpus = aml_name(CPU_EJ_LIST);
+ Aml *num_ej_cpus = aml_local(5);
aml_append(method, aml_acquire(ctrl_lock, 0xFFFF));
@@ -513,6 +515,8 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
*/
aml_append(method, aml_name_decl(CPU_ADDED_LIST,
aml_package(max_cpus_per_pass)));
+ aml_append(method, aml_name_decl(CPU_EJ_LIST,
+ aml_package(max_cpus_per_pass)));
aml_append(method, aml_store(zero, uid));
aml_append(method, aml_store(one, has_job));
@@ -527,6 +531,7 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
aml_append(while_ctx2, aml_store(one, has_event));
aml_append(while_ctx2, aml_store(zero, num_added_cpus));
+ aml_append(while_ctx2, aml_store(zero, num_ej_cpus));
/*
* Scan CPUs, till there are CPUs with events or
@@ -559,8 +564,10 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
* if CPU_ADDED_LIST is full, exit inner loop and process
* collected CPUs
*/
- ifctx = aml_if(
- aml_equal(num_added_cpus, aml_int(max_cpus_per_pass)));
+ ifctx = aml_if(aml_lor(
+ aml_equal(num_added_cpus, aml_int(max_cpus_per_pass)),
+ aml_equal(num_ej_cpus, aml_int(max_cpus_per_pass))
+ ));
{
aml_append(ifctx, aml_store(one, has_job));
aml_append(ifctx, aml_break());
@@ -577,16 +584,16 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
aml_append(ifctx, aml_store(one, has_event));
}
aml_append(while_ctx, ifctx);
- else_ctx = aml_else();
+
ifctx = aml_if(aml_equal(rm_evt, one));
{
- aml_append(ifctx,
- aml_call2(CPU_NOTIFY_METHOD, uid, eject_req));
- aml_append(ifctx, aml_store(one, rm_evt));
+ /* cache to be removed CPUs to Notify later */
+ aml_append(ifctx, aml_store(uid,
+ aml_index(ej_cpus, num_ej_cpus)));
+ aml_append(ifctx, aml_increment(num_ej_cpus));
aml_append(ifctx, aml_store(one, has_event));
}
- aml_append(else_ctx, ifctx);
- aml_append(while_ctx, else_ctx);
+ aml_append(while_ctx, ifctx);
aml_append(while_ctx, aml_increment(uid));
}
aml_append(while_ctx2, while_ctx);
@@ -620,6 +627,24 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
aml_append(while_ctx, aml_increment(cpu_idx));
}
aml_append(while_ctx2, while_ctx);
+
+ /*
+ * Notify OSPM about to be removed CPUs and clear remove flag
+ */
+ aml_append(while_ctx2, aml_store(zero, cpu_idx));
+ while_ctx = aml_while(aml_lless(cpu_idx, num_ej_cpus));
+ {
+ aml_append(while_ctx,
+ aml_store(aml_derefof(aml_index(ej_cpus, cpu_idx)),
+ uid));
+ aml_append(while_ctx,
+ aml_call2(CPU_NOTIFY_METHOD, uid, eject_req));
+ aml_append(while_ctx, aml_store(uid, cpu_selector));
+ aml_append(while_ctx, aml_store(one, rm_evt));
+ aml_append(while_ctx, aml_increment(cpu_idx));
+ }
+ aml_append(while_ctx2, while_ctx);
+
/*
* If another batch is needed, then it will resume scanning
* exactly at -- and not after -- the last CPU that's currently
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 05/48] tests: acpi: update expected blobs
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (3 preceding siblings ...)
2025-01-15 18:08 ` [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec Michael S. Tsirkin
` (45 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Igor Mammedov, Eric Mackay, Ani Sinha
From: Igor Mammedov <imammedo@redhat.com>
previous patch has changed cpu hotplug AML, expected diff:
@@ -2942,6 +2942,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
+ Name (CEJL, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
@@ -2949,6 +2950,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
Local4 = Zero
Local0 = One
Local1 = Zero
+ Local5 = Zero
While (((Local0 == One) && (Local3 < One)))
{
Local0 = Zero
@@ -2959,7 +2961,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
Break
}
- If ((Local1 == 0xFF))
+ If (((Local1 == 0xFF) || (Local5 == 0xFF)))
{
Local4 = One
Break
@@ -2972,10 +2974,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
Local1++
Local0 = One
}
- ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+
+ If ((\_SB.PCI0.PRES.CRMV == One))
{
- CTFY (Local3, 0x03)
- \_SB.PCI0.PRES.CRMV = One
+ CEJL [Local5] = Local3
+ Local5++
Local0 = One
}
@@ -2992,6 +2995,16 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
\_SB.PCI0.PRES.CINS = One
Local2++
}
+
+ Local2 = Zero
+ While ((Local2 < Local5))
+ {
+ Local3 = DerefOf (CEJL [Local2])
+ CTFY (Local3, 0x03)
+ \_SB.PCI0.PRES.CSEL = Local3
+ \_SB.PCI0.PRES.CRMV = One
+ Local2++
+ }
}
Release (\_SB.PCI0.PRES.CPLK)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20241210163945.3422623-4-imammedo@redhat.com>
Tested-by: Eric Mackay <eric.mackay@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 42 ------------------
tests/data/acpi/x86/pc/DSDT | Bin 8526 -> 8593 bytes
tests/data/acpi/x86/pc/DSDT.acpierst | Bin 8437 -> 8504 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat | Bin 9851 -> 9918 bytes
tests/data/acpi/x86/pc/DSDT.bridge | Bin 15397 -> 15464 bytes
tests/data/acpi/x86/pc/DSDT.cphp | Bin 8990 -> 9057 bytes
tests/data/acpi/x86/pc/DSDT.dimmpxm | Bin 10180 -> 10247 bytes
tests/data/acpi/x86/pc/DSDT.hpbridge | Bin 8477 -> 8544 bytes
tests/data/acpi/x86/pc/DSDT.hpbrroot | Bin 5033 -> 5100 bytes
tests/data/acpi/x86/pc/DSDT.ipmikcs | Bin 8598 -> 8665 bytes
tests/data/acpi/x86/pc/DSDT.memhp | Bin 9885 -> 9952 bytes
tests/data/acpi/x86/pc/DSDT.nohpet | Bin 8384 -> 8451 bytes
tests/data/acpi/x86/pc/DSDT.numamem | Bin 8532 -> 8599 bytes
tests/data/acpi/x86/pc/DSDT.roothp | Bin 12319 -> 12386 bytes
tests/data/acpi/x86/q35/DSDT | Bin 8355 -> 8422 bytes
tests/data/acpi/x86/q35/DSDT.acpierst | Bin 8372 -> 8439 bytes
tests/data/acpi/x86/q35/DSDT.acpihmat | Bin 9680 -> 9747 bytes
.../data/acpi/x86/q35/DSDT.acpihmat-generic-x | Bin 12565 -> 12632 bytes
.../acpi/x86/q35/DSDT.acpihmat-noinitiator | Bin 8634 -> 8701 bytes
tests/data/acpi/x86/q35/DSDT.applesmc | Bin 8401 -> 8468 bytes
tests/data/acpi/x86/q35/DSDT.bridge | Bin 11968 -> 12035 bytes
tests/data/acpi/x86/q35/DSDT.core-count | Bin 12913 -> 12980 bytes
tests/data/acpi/x86/q35/DSDT.core-count2 | Bin 33770 -> 33837 bytes
tests/data/acpi/x86/q35/DSDT.cphp | Bin 8819 -> 8886 bytes
tests/data/acpi/x86/q35/DSDT.cxl | Bin 13146 -> 13213 bytes
tests/data/acpi/x86/q35/DSDT.dimmpxm | Bin 10009 -> 10076 bytes
tests/data/acpi/x86/q35/DSDT.ipmibt | Bin 8430 -> 8497 bytes
tests/data/acpi/x86/q35/DSDT.ipmismbus | Bin 8443 -> 8510 bytes
tests/data/acpi/x86/q35/DSDT.ivrs | Bin 8372 -> 8439 bytes
tests/data/acpi/x86/q35/DSDT.memhp | Bin 9714 -> 9781 bytes
tests/data/acpi/x86/q35/DSDT.mmio64 | Bin 9485 -> 9552 bytes
tests/data/acpi/x86/q35/DSDT.multi-bridge | Bin 13208 -> 13275 bytes
tests/data/acpi/x86/q35/DSDT.noacpihp | Bin 8235 -> 8302 bytes
tests/data/acpi/x86/q35/DSDT.nohpet | Bin 8213 -> 8280 bytes
tests/data/acpi/x86/q35/DSDT.numamem | Bin 8361 -> 8428 bytes
tests/data/acpi/x86/q35/DSDT.pvpanic-isa | Bin 8456 -> 8523 bytes
tests/data/acpi/x86/q35/DSDT.thread-count | Bin 12913 -> 12980 bytes
tests/data/acpi/x86/q35/DSDT.thread-count2 | Bin 33770 -> 33837 bytes
tests/data/acpi/x86/q35/DSDT.tis.tpm12 | Bin 8961 -> 9028 bytes
tests/data/acpi/x86/q35/DSDT.tis.tpm2 | Bin 8987 -> 9054 bytes
tests/data/acpi/x86/q35/DSDT.type4-count | Bin 18589 -> 18656 bytes
tests/data/acpi/x86/q35/DSDT.viot | Bin 14612 -> 14679 bytes
tests/data/acpi/x86/q35/DSDT.xapic | Bin 35718 -> 35785 bytes
43 files changed, 42 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index a1047913af..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,43 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/x86/pc/DSDT",
-"tests/data/acpi/x86/pc/DSDT.acpierst",
-"tests/data/acpi/x86/pc/DSDT.acpihmat",
-"tests/data/acpi/x86/pc/DSDT.bridge",
-"tests/data/acpi/x86/pc/DSDT.cphp",
-"tests/data/acpi/x86/pc/DSDT.dimmpxm",
-"tests/data/acpi/x86/pc/DSDT.hpbridge",
-"tests/data/acpi/x86/pc/DSDT.hpbrroot",
-"tests/data/acpi/x86/pc/DSDT.ipmikcs",
-"tests/data/acpi/x86/pc/DSDT.memhp",
-"tests/data/acpi/x86/pc/DSDT.nohpet",
-"tests/data/acpi/x86/pc/DSDT.numamem",
-"tests/data/acpi/x86/pc/DSDT.roothp",
-"tests/data/acpi/x86/q35/DSDT",
-"tests/data/acpi/x86/q35/DSDT.acpierst",
-"tests/data/acpi/x86/q35/DSDT.acpihmat",
-"tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x",
-"tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator",
-"tests/data/acpi/x86/q35/DSDT.applesmc",
-"tests/data/acpi/x86/q35/DSDT.bridge",
-"tests/data/acpi/x86/q35/DSDT.core-count",
-"tests/data/acpi/x86/q35/DSDT.core-count2",
-"tests/data/acpi/x86/q35/DSDT.cphp",
-"tests/data/acpi/x86/q35/DSDT.cxl",
-"tests/data/acpi/x86/q35/DSDT.dimmpxm",
-"tests/data/acpi/x86/q35/DSDT.ipmibt",
-"tests/data/acpi/x86/q35/DSDT.ipmismbus",
-"tests/data/acpi/x86/q35/DSDT.ivrs",
-"tests/data/acpi/x86/q35/DSDT.memhp",
-"tests/data/acpi/x86/q35/DSDT.mmio64",
-"tests/data/acpi/x86/q35/DSDT.multi-bridge",
-"tests/data/acpi/x86/q35/DSDT.noacpihp",
-"tests/data/acpi/x86/q35/DSDT.nohpet",
-"tests/data/acpi/x86/q35/DSDT.numamem",
-"tests/data/acpi/x86/q35/DSDT.pvpanic-isa",
-"tests/data/acpi/x86/q35/DSDT.thread-count",
-"tests/data/acpi/x86/q35/DSDT.thread-count2",
-"tests/data/acpi/x86/q35/DSDT.tis.tpm12",
-"tests/data/acpi/x86/q35/DSDT.tis.tpm2",
-"tests/data/acpi/x86/q35/DSDT.type4-count",
-"tests/data/acpi/x86/q35/DSDT.viot",
-"tests/data/acpi/x86/q35/DSDT.xapic",
diff --git a/tests/data/acpi/x86/pc/DSDT b/tests/data/acpi/x86/pc/DSDT
index 8b8235fe79e2fa08a6f840c8479edb75f5a047b9..60d50b088a362556fd54395cb15364d6c0936be5 100644
GIT binary patch
delta 191
zcmX@-G|`#MCD<ioq9OwWqy0v%ojgoV&XbSwY+!P*m|V{Lm)%p!IoR2cW3nutxHgBg
zpKG`f(|-<US1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DR^U&zFO5;^aiG
z|C3WEGx0kpEl`;pqt6l_>=Ym1>}e1X<QnW8<Qv9VklX<>EtR1(b#ghspHu-u(jq68
psY$5?&0vWnhGgdux5#8J=E*bp)mejl!%CAT$MK16zRh1O2mpbPI&}a5
delta 140
zcmV;70CWG5L(W19L{mgmP9XpQ0co)cxeNkNK9j`^umVjplXngM2Sye{Q$tP&lN}Bh
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43oVMO#=y&VUrRMKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Imhz4;7Pi4^ER_4i>W>5OWbzU?~#-
diff --git a/tests/data/acpi/x86/pc/DSDT.acpierst b/tests/data/acpi/x86/pc/DSDT.acpierst
index 06829b9c6c6d726d955dc7c99bc9f42448e22aeb..4c434c25c0b1602f22128e352781df498fa69ddf 100644
GIT binary patch
delta 191
zcmezBxWkFdCD<jzLXm-iv3(=gP97#F=gCKTHZVC@OfKjB%kC-V9PI4JF<F*RT${t$
z&ox|#=|6|FtCx=u)Bgg7<O0T&MgF3bQy2>vQVJLo3K$X#7*ZGcaZldF=gYx2adINp
z|H-M7nfM))7N|^)(PxPdc8U*h_B03xat(G4@(p7wNbUfcmda3?I=P(RPpW_+X^|7l
p)TGpcX0SvOL$Y&-TVyg9^W>TQ>a0P&VWmlv<M_lj-{zMR1OThaI#&Py
delta 140
zcmV;70CWGiLiIrkL{mgm^&kKM0kW|QxeNkNK9j`^umVjplXngM2Sye{Q$tP&lN}Bh
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43oVMO#=y&VUrRMKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Imhz4;7Pi4^ER_4i>W>5E>Em)hYD=
diff --git a/tests/data/acpi/x86/pc/DSDT.acpihmat b/tests/data/acpi/x86/pc/DSDT.acpihmat
index 2fe355ebdbb858fa9247d09112e21712e3eddc45..61b7d5caa55c44dbf69d649110c6b14bb4c3fdf5 100644
GIT binary patch
delta 175
zcmezEv(J~yCD<iopBe)L<DZROJ9(HKJtrUK*}&v)ySbc~gOSNgYH}l=iZX|@tCx=u
z)Bgg7<O0T&MGj(<Qy2>vQVJLo3K$X#7*ZGcb5GvO=f}Y}adINp|H-M7`S=}_7N|^)
z(PxPdc8U*h_B03xat(G4@(p7wNbUfcmda3?I=PwOPo{t&X^|7l)TGpcX0SvOL$Y&-
ZTVyg9b3yWCM?O{NAm6af=lR!&0RY%RHrfCH
delta 117
zcmV-*0E+*<P5Vp=L{mgmdnNz?0Vc5uxeNkMM3cn~umVguvv&;$0Rl%BlYtH-7;pe%
zZ~<hZMG})_0dN3hZ~<U&0AZp{43o$XP6G*(VUr#YKm?&Tpf!_V4;2YRR7P223IlKf
XlVJ}NlYkFS0$V4O!3`6$DG-$w=m8<V
diff --git a/tests/data/acpi/x86/pc/DSDT.bridge b/tests/data/acpi/x86/pc/DSDT.bridge
index 4d4067c182a6625db1e877408eb7436113884b50..d43e148bed19160f39d88ccf3364544150a3f87f 100644
GIT binary patch
delta 191
zcmZ2l@uGsuCD<h-!-j!@(RU-)P97#F=gCKTHZVC@OfKjB%kC-V9PI4JF<F*RT${t$
z&ox|#=|6|FtCx=u)Bgg7<O0T&MgF3bQy2>vQVJLo3K$X#7*ZGcaZldF=gYx2adINp
z|H-M7nfM))7N|^)(PxPdc8U*h_B03xat(G4@(p7wNbUfcmda3?I=P(RPpW_+X^|7l
p)TGpcX0SvOL$Y&-TVyg9^W>TQ>a0P&VWmlv<M_lj-{$wy0RZuvI{*Lx
delta 140
zcmV;70CWH7c%^s>L{mgmB|HEC0e7(qxeNkNK9j`^umVjplXngM2Sye{Q$tP&lN}Bh
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43oVMO#=y&VUrRMKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Imhz4;7Pi4^ER_4i>W>5K1hi?<t-D
diff --git a/tests/data/acpi/x86/pc/DSDT.cphp b/tests/data/acpi/x86/pc/DSDT.cphp
index 045a52e75b7fcd4e5f840a758c548231498b96e4..9fda0b56638e02097e58dd4536c9c5955986e88e 100644
GIT binary patch
delta 167
zcmbQ|_Rx*XCD<h-QJH~(annYwojgoV36qcVY+!N--CWLV$;j>{<s9tn$1(W>ulVG1
zd>qOg&aPfQLQMY)7?KMZQx-XhO-^AfU`Q!oOekPTEMQ1o<j+0%9iJZu-^9s@T>mGh
zPPXTFU|ygydGbPjVIIbU<PMPjREE;j$y@mSqzV|47CEs@O-e0j21_I{Bs+(=MJ97G
RPrk;l&K%?$wn;!v7yuUwG#~%~
delta 134
zcmV;10D1r6MxI6rL{mgm9wPt%0nM=rxeNkNTa(2MumVj`vv&<S0S8AGLsLUe2$S#)
z7n9Bo2pDhxV{idvqD2yuWC3shWN-msZ~$SVO$?Ly4o(9JlVOuj4?qN=H=s3>kq;Fd
oLsUjtV+sRs0bDNxUsFO~P(w*DP*O!xLsCsvld%s@vqcab6Skcv^Z)<=
diff --git a/tests/data/acpi/x86/pc/DSDT.dimmpxm b/tests/data/acpi/x86/pc/DSDT.dimmpxm
index 205219b99d903555125c4b07fc047c42993eb338..5b6471c8db9003b39bf5e20af34061f3e71cdbd5 100644
GIT binary patch
delta 173
zcmX@&-yXo_66_MfuED^-7{8J0EDw`+$mE+m8<;#jH+S<YFfw^bO<v2VqRip!>g6NE
z^uK^1xqvZck%QRe6vhIElmf<t0*1r_hSWv=+>>AO`El?~oSew@e{$+%D}D#11uBzc
z^jYGAo#F$WJq-eaT!Wp1e8U(Ek~=`Ar81PJPF~ONCsn|Zw8)8NYEo)JGgu;tA=x>^
XEi##ldGbYmb><-7u+6{uPl^Ko(i=8M
delta 141
zcmZn<IO5Oc66_LkM4f?wapp#@vph^50h4d?Y+!P8-Q3Nqz{un-HhC?dibMfJasgw?
zB3GfwDU1aSDFuuP1q_Lce0e5+;qznWoSZn>i{HU?q4@&S$uasY@xe~<0nVNV0YR?8
e&OyFmjLso$k;z=l1&mlEC$Hi6+w354TpR%WuPVd<
diff --git a/tests/data/acpi/x86/pc/DSDT.hpbridge b/tests/data/acpi/x86/pc/DSDT.hpbridge
index 8fa8b519ec65bd5099c45f4e1c85b11b47a23845..67fe28699fbb261cfc7a52b2291f9965ab93c6a8 100644
GIT binary patch
delta 191
zcmbR1^uUSBCD<h-L6L!hv3MibP97#F=gCKTHZVC@OfKjB%kC-V9PI4JF<F*RT${t$
z&ox|#=|6|FtCx=u)Bgg7<O0T&MgF3bQy2>vQVJLo3K$X#7*ZGcaZldF=gYx2adINp
z|H-M7nfM))7N|^)(PxPdc8U*h_B03xat(G4@(p7wNbUfcmda3?I=P(RPpW_+X^|7l
p)TGpcX0SvOL$Y&-TVyg9^W>TQ>a0P&VWmlv<M_lj-{yA`1OS&)I%EI<
delta 140
zcmV;70CWG~LY+biL{mgm9U%Y!0iCf5xeNkNK9j`^umVjplXngM2Sye{Q$tP&lN}Bh
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43oVMO#=y&VUrRMKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Imhz4;7Pi4^ER_4i>W>5JC}S!YKj(
diff --git a/tests/data/acpi/x86/pc/DSDT.hpbrroot b/tests/data/acpi/x86/pc/DSDT.hpbrroot
index 01719462a72fd6d40ce433dac601e4b94eae574c..077a4cc988dc417a1bc9317dddd2dbd96ff1ff50 100644
GIT binary patch
delta 195
zcmZ3f{zje4CD<k8jW7cPWAa9>9Bw8j=gAe^8<-p{CTsEhW%rbF4tDnAn0$dpT${t$
z&ox|#=|6|FtCx=u)Bgg7<O0T&MgF3bQy2>vQVJLo3K$X#7*ZGcaZgU=_2uB3I60B)
z|K!xkTX`Ln7N|^)(PxPdc8U*h_B03xat(G4@(p7wNbUfcmda3?I$4X)PpW_+X^|7l
t)TGpcX0SvOL$Y&-TVyg9^W=P9vB`gV1X+W8!%CAT3-XF>?&FhY1pt{dJ23zN
delta 157
zcmaE(zEYjbCD<ior7!~nWA8?;9Bw9myU7*Y8<>2JCu{NiWp@*E4tDnAn0$dpT!F*c
z&ox|#>3;!3asgw?A{U{_DU1aSDFuuP1q_Lce0U}o@cJ@yPEMSBl-I#@q4@&S$uasY
u@xe~<0nVNV0YR?8&OyFmjLso$k;z=l1&mlEC#&=MO%~)8+kBBvniT*|<t>~5
diff --git a/tests/data/acpi/x86/pc/DSDT.ipmikcs b/tests/data/acpi/x86/pc/DSDT.ipmikcs
index 0ca664688b16baa3a06b8440181de4f17511c6b0..9b2e81a7bcefb5c0e2dfbd2bbc5b6ea501f86306 100644
GIT binary patch
delta 191
zcmbQ{eAAiBCD<k8rXm9a<L-@IJ9(I#oF^aU*}&vrF}a-gFT1CdbFi}?$7ESPacvG~
zKi6;}rvDtyu3kPuO#cfQk_#A97Ws=#PGKxyNGV`UC}2n|U`So$$31xypDzdB#L0<V
z|0kzTX5x2HTA(sHMxP}<*eO21+0!5($TiqG$Ty6!Ah`o%S}H?n>f~~MKdAzSq(x3F
pQ<G8)n!yrD49U(RZjs4c%#&yGtFs3AhLt8wj^h*Ce4Br_AOIIQJCXnZ
delta 140
zcmV;70CWG@LzY7dL{mgmmLUKD0p+m@xeNkNK9j`^umVjplXngM2Sye{Q$tP&lN}Bh
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43oVMO#=y&VUrRMKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Imhz4;7Pi4^ER_4i>W>5W5k-i7GGv
diff --git a/tests/data/acpi/x86/pc/DSDT.memhp b/tests/data/acpi/x86/pc/DSDT.memhp
index 03ff464ba4e72082fce0921815cfc09ca20b561a..9c66ccf150af1622d1b788a1ae04a6e5136cff9e 100644
GIT binary patch
delta 191
zcmbR1`@omWCD<k8ff@q?qwq$qojgn)&XbSwY+!P;m|V{Lm)%p!IoR2cW3nutxHgBg
zpKG`f(|-<US1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DR^U&zFO5;^aiG
z|C3WEGx0kpEl`;pqt6l_>=Ym1>}e1X<QnW8<Qv9VklX<>EtR1(b#ghspHu-u(jq68
psY$5?&0vWnhGgdux5#8J=E*bp)mejl!%CAT$MK16zRiC~3;@iTJ1_tM
delta 140
zcmV;70CWG~O`S~&L{mgmohASP0b8*OxeNkDKa<4_umVFglXngM2Sye{Q$tP&lN}Bh
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43oVMO#=y&VUrRMKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Imhz4;7Pi4^ER_4i>W>5W*IV{wdA?
diff --git a/tests/data/acpi/x86/pc/DSDT.nohpet b/tests/data/acpi/x86/pc/DSDT.nohpet
index b081030f0ed171e52b13e28cfdc8770a04c2806e..28dbd8d8949d1421da9312cf0440d7ae3b64916e 100644
GIT binary patch
delta 195
zcmX@$*zCmR66_MftjNH?$gz=2n}^BCd9pdr1||oK$uD{SvU^H72Rr+5Oz!6u*XD5c
za}5__`p@C)>g6NE^uK^1xqvZck-zBV6vhIElmf<t0*1r_hSWuV+>=%Kd^z|gPEO?d
zKRI=B37><~0+q=z`YiFmPVoWGo(2IyuEEYhzF~|7$sHimQW;89C%@$LlPX|HTI9qs
tH7T{A87z^+kn9}d7MaY&JXw!VZ1NsnLDnGOu+pT-7kI@s`|=kH0sxakI)4BF
delta 157
zcmZp6I^f9V66_LkK!JgQ(Rd@5HV>1(-DGo~4NShqlV9@uWp@*E4tDnAnB31RuE62!
z=Nc}=^uK^1xqvZck&Dpe6vhIElmf<t0*1szK0K54`Fxo<CnrvB;d3xuXuiO7a*RGp
ue6Uk|fU~DTK#*&&bC7QsqjQK`WHJ|X0V5X4$<O%wCSTwc+dP54SP%dOB`#_J
diff --git a/tests/data/acpi/x86/pc/DSDT.numamem b/tests/data/acpi/x86/pc/DSDT.numamem
index 2c98cafbff5db04410b35a1151eaf18723a4dad7..e256bbce790152f045247db631d9f1da81f90499 100644
GIT binary patch
delta 191
zcmccOG~JoYCD<iox*`Ju<LQlDJ9(HqoF^aU*}&vxF}a-gFT1CdbFi}?$7ESPacvG~
zKi6;}rvDtyu3kPuO#cfQk_#A97Ws=#PGKxyNGV`UC}2n|U`So$$31xypDzdB#L0<V
z|0kzTX5x2HTA(sHMxP}<*eO21+0!5($TiqG$Ty6!Ah`o%S}H?n>f~~MKdAzSq(x3F
pQ<G8)n!yrD49U(RZjs4c%#&yGtFs3AhLt8wj^h*Ce4D>g5CHdWJ0$=B
delta 140
zcmV;70CWGBL)1bFL{mgmR3QKW0TZzbxeNkDKa<4_umVFglXngM2Sye{Q$tP&lN}Bh
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43oVMO#=y&VUrRMKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Imhz4;7Pi4^ER_4i>W>5P1<Qdnm&I
diff --git a/tests/data/acpi/x86/pc/DSDT.roothp b/tests/data/acpi/x86/pc/DSDT.roothp
index da018dca9e3102e811107994248719ab5278c505..0557810ddc18dc280d039163c72b25428a2486c1 100644
GIT binary patch
delta 191
zcmbQA@F;=HCD<h-$$)`@@$^QnojgoV&XbSwY+!P*m|V{Lm)%p!IoR2cW3nutxHgBg
zpKG`f(|-<US1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DR^U&zFO5;^aiG
z|C3WEGx0kpEl`;pqt6l_>=Ym1>}e1X<QnW8<Qv9VklX<>EtR1(b#ghspHu-u(jq68
psY$5?&0vWnhGgdux5#8J=E*bp)mejl!%CAT$MK16zRmBV000k|J01W4
delta 140
zcmV;70CWH1V4q+LL{mgmA20v_0rjy8xeNkNK9j`^umVjplXngM2Sye{Q$tP&lN}Bh
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43oVMO#=y&VUrRMKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Imhz4;7Pi4^ER_4i>W>5JVulO)0zp
diff --git a/tests/data/acpi/x86/q35/DSDT b/tests/data/acpi/x86/q35/DSDT
index fb89ae0ac6d4346e33156e9e4d3718698a0a1a8e..51ad37a351bffae8fbc9ba17f72c25ef61822f59 100644
GIT binary patch
delta 180
zcmZ4N_{@>ZCD<k8nF0d?Bkx8oc1b2D=gGp78<-p{CLfjj%kC-V9PI4JG1)*yeDVV+
z4rLB!S1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DMk#%fUBsaw6CN$*GeA
zq#cwNs7#L0XNeDXiVtx1GzbWC4R#Ll4Pz`w?f@B<%21j*`KYv?Q~^WMA}5xqNvQ?R
eV2LD#WakjK$Yd_&$<L+LnS*@8HVev3VgUdW&^H4B
delta 109
zcmV-z0FwXaL8CzmL{mgmqaXkP0XMM<2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRveH7+b|#D
diff --git a/tests/data/acpi/x86/q35/DSDT.acpierst b/tests/data/acpi/x86/q35/DSDT.acpierst
index 46fd25400b7c00ee9149ddb64cb5d5bd73f6a82b..dbd4f858354df0f4c050fd0b914581154f340ee8 100644
GIT binary patch
delta 180
zcmdnu_}!7qCD<k8y8;6P<Jyf}?2=4Q&Xa{DH!wL^Og<|4m)%p!IoR2cW3qva_~Zvt
z9LgNdu3kPuO#cfQk_#A97Ws=#PGKxyNGV`UC}2n|U`So$$302fmxFKO<V3FjlT#-L
zNINJkP?;Q~&k`T(6d&O1X%G<P8tfe88^&0W+yOEym7z3s@=<9&sRD+iMNTYJlTr(s
e!4gRf$<85ek;z=llb=hgGY9#GZ5EVS%mM(N(>Lb;
delta 109
zcmV-z0FwXrL9{^%L{mgmv>*Tg0oSn#2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRve)OE4?7a
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat b/tests/data/acpi/x86/q35/DSDT.acpihmat
index 61c5bd52a42242e85090934e8e45bf01642609d6..952752e30e9dfc9e2085e8fceaa0740dda6db89c 100644
GIT binary patch
delta 159
zcmccMJ=urLCD<iISdD>!@#ID>c1b2j&&k4)8<_lUHy@ScU}W-=ntWbLMVZ6d)yqeS
z>3;!3asgw?A_uX_DU1aSDFuuP1q_J=45^F!xhHc=`*HA1oSew@e{$;N7-<Kl1uByl
zNQ-h8BzJ&xr!thLPQEDZCsV+Xw8)8NYEo)JGgu;tA=x>^Ei##lxgdFRzmzI-kZ;&#
IS((k80E*WzCIA2c
delta 141
zcmbR2bHSU-CD<k8f+_<8<Cl$G?2=4=E|Y~NH!%5FZayl>!N}w;Hu=1iibMfJasgw?
zB3GfwDU1aSDFuuP1q_Lce0e5|N&7K#PEMShBkf?i(0qaE<QRRH_+Y2_0B28wfFRdk
e=OEuOM&}T>$Yd_&0!A#7lg~-}ZBCNe$O!;@8!4;+
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x b/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x
index 497706c9742a9ea5396d6c9c4cc1cc2a4a530339..e95258cbd8681103a642f8973bd1ac9ef229cff7 100644
GIT binary patch
delta 173
zcmbQ5bR&t&CD<h-!jOT1F>fOmyCjpp-(+FQ4NShyn~zG0Ffw^bO};IqqRip!>g6NE
z^uK^1xqvZck%QRe6vhIElmf<t0*1r_hSWv=+>^zn{W$n0PEO?dKRI=BhO~py0+q=z
z`YiFmPVoWGo(2IyuEEYhzF~|7$sHimQW;89C*PI!lPX|HTI9qsH7T{A87z^+kn9}d
W7MaY&Jo&%0I&+Y3*k(<cHzELbaWy#r
delta 141
zcmcbSG&PCKCD<iI)R2LJars6rc1b25ugSua8<@Q8Hy@Q0VPtX_n|xbJMWTQqxqvZc
zk*m<;6vhIElmf<t0*1szzC4qar2UvVCnrv>kajR#XuiO7a*RGpe6Uk|fU~DTK#*&&
ebC7QsqjQK`WHJ|X0V5X4$+x8aHs{H_5&-}%Gbwuj
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator b/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
index 3aaa2bbdf54a0d0cade14421e84c6ec5a42f96fa..ba2a7d0004be7cd7220716dc7e8594be87197b98 100644
GIT binary patch
delta 200
zcmdnx{MVVwCD<k8uOb5jW6MS^c1b4BkjcW58<^ZZHy@Q$VC3|Yat?O(<A_$CTqq^1
z`~N?Ov!83Y5YvASXIC#DA*TNY49NwIDT^G$CZ{kKFr*YPCKNCv7BHkP^5>qcEbYg^
zH*s<z*Z;|>lS`x>loqH=j?rg{4|a+VaP~9^2yzW}4)P6SEJ*GEnU=~>nmYNVw4YP~
yL((EAmZ?dp1<hcIB!*<?5Vy!=F6PO4(qfZ$O9`?D`G%DyO+GIrw%J!EmlXghfj&V1
delta 162
zcmezCyvv!(CD<iomm&iL<KB&2?2=4w0h5I#H!!)lZaylhz{u$?<{a$o#}TbOxll@2
z>HmKYXFu0)A*TNY49NwIDT`c%CZ{kKFr*YPCKNCvF7oA>tS9Zq%sDx6a*MQs=|b}b
zrjujzS>l78;scyL4FZB(gPntX!x)`I+#-{?m<t%ONKSqx?Kk<nl-TA8GP$e(dgCz@
diff --git a/tests/data/acpi/x86/q35/DSDT.applesmc b/tests/data/acpi/x86/q35/DSDT.applesmc
index 944209adeaa5bbb722431161c404cb51b8209993..b6cb840953ea539092f601e08b7122fc999b3e1b 100644
GIT binary patch
delta 180
zcmccUIK_#}CD<iIM3I4k@y|vsc1b2D=gGp78<-p{CLfjj%kC-V9PI4JG1)*yeDVV+
z4rLB!S1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DMk#%fUBsaw6CN$*GeA
zq#cwNs7#L0XNeDXiVtx1GzbWC4R#Ll4Pz`w?f@B<%21j*`KYv?Q~^WMA}5xqNvQ?R
eV2LD#WakjK$Yd_&$<L+LnS*@8HVeueU;zLMk2fp;
delta 109
zcmV-z0FwWdLeW7AL{mgm(I5Z-0VlBv2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvf+r*iaw}
diff --git a/tests/data/acpi/x86/q35/DSDT.bridge b/tests/data/acpi/x86/q35/DSDT.bridge
index d9938dba8fa5d405f7696c0dbdc24f3ae42ec934..1939fda2507cde6fcb6f7a093897f9bd2cb987ef 100644
GIT binary patch
delta 180
zcmX>Q+Z@N`66_Mftk1x}sIifYU6RSkd9twN1||oK$wwvsvU^H72Rr+5Og4}apZq|I
zLz%<b)yqeS>3;!3asgw?B7f1zDU1aSDFuuP1q_J=45^F!xF<>ba_~)@oXGWma_Zy&
zX$PeRDwAXMS>l78;scyL4FZB(gPntX!x#&aJ3xk|GL)uHJ}T`eRltz6$cbfYQffgn
dSR#ob**U~5GMS5c@^fi*<{;m&&4M!Pg#eBZHfR6<
delta 109
zcmV-z0FwWMUcg-nL{mgmz%Bp)0aLLG2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvfJo@Ma)J
diff --git a/tests/data/acpi/x86/q35/DSDT.core-count b/tests/data/acpi/x86/q35/DSDT.core-count
index a24b04cbdbf09383b933a42a2a15182545543a87..41c0832ab5041ff5361598813ec28fe7442b191b 100644
GIT binary patch
delta 168
zcmeyEvL%(vCD<ioixC3@W9vpPc1fm&gvr8^8<~1THXoC$VrKV}at?O(<CxqaBR)A!
zmP47t+11NOi0OX;LvjIQ$|47`$tjEl3@HVS2?Y#^1q`W+{JAIB$@+2dO`M#_^?!2e
z<nyu)%nMW|Pd1bj=3y*I?f~geWhhOZ>>}qURltz6$cbfYQffgnSR#ob**U~5GMS5c
Ra+;hvbC7S?<_U5Sg#j0XG*JKm
delta 134
zcmV;10D1qkW$|PRL{mgmaWVh^0k5$N2N?p5TayzRu>y)vv&I>E0|!SILsLUe2$O&u
z7n5Ec2pDhxV{idvqD2yuWC3shWN-msZ~$SVO$?KX9ZmxYlVOwJ9Y6%3H=s3>As!VR
oLsUjtV+sRs0bDNxUsFO~P(w*DP*O!xLsCsvlR+L%v(+Bo6Qh?Xg#Z8m
diff --git a/tests/data/acpi/x86/q35/DSDT.core-count2 b/tests/data/acpi/x86/q35/DSDT.core-count2
index 3a0cb8c581c8cc630a2ec21712b7f8b75fcad1c8..153b45f0f7443d25cecc2a752fb6dbd921160e78 100644
GIT binary patch
delta 160
zcmaFW&a}3JiOVI}B}BJ{fr0VbMlN<qrq1%o!jc=A+Hy7@lT_nn@|K$XPEAFL!`ao#
zM~LZv0Yh>DW6B~&vB@cn1q>+#j0pt{i3JR)iyS6vst0iJO`M#_^?!2e<QjDcrUfdK
z52%ZB7bJIpG^a9@rcVB-?k7{gkhI8&WolAtK{Hq)i6PlJ#4R$Ji@6|q@;WtD<{;m&
J&9)kAqXG4WGspk{
delta 142
zcmZ46!St$~iOVI}CFE5z0|O)DMlN<qrnchA!jc=Anlm;ZlT_nn@(`Q+PEAF;fFZen
zF=dgP(Bu@x0)~_V#)JZf#6^CSP1FOJIVUGh?ooFzU1+|*baIS7OMI|Xe1Nm3K|qje
fuyc@a7^8EDTVyg9a{(h3$;t23{Wdpgtd0f%C_O9p
diff --git a/tests/data/acpi/x86/q35/DSDT.cphp b/tests/data/acpi/x86/q35/DSDT.cphp
index 20955d0aa30120553da35d5a6640055d26255cf9..231bc23d932e832ffa12dd253bcf54245b5ef88f 100644
GIT binary patch
delta 158
zcmezDvdxvtCD<ion-T*9W5Y%+c1b3ugvr8^8<-qIHy@R>WMuM^nk22F%;D_n<s-!O
zzkngRfH7r}gV^L0#sY?v0>*>_hQtDf)J6W>lWnB^IQS+`PUQMOIdyWcv;)%umB|;S
zMY#)-J3zWq8A?+pGs*bL6fh($a$=d9lv>aXmPleqb`EiiOy*)PNS=H^N|iatH*B+?
Hj4B%dq#Q5J
delta 124
zcmV-?0E7RwMe{@oL{mgmb0Po$0h_T32N?oSTayzRumVj`v&9)X0Rl%Bk{cu#Z~$X)
z0c4^@5|d;BZ~$a*0bp<dVWLe8lSdm)0|}F1lbstt1fe&eHIv^P6&yoUMp<JD18@Oc
eF9csxLSIlrNia}SMN>mkO;(ft8&0#693uw7dL)Se
diff --git a/tests/data/acpi/x86/q35/DSDT.cxl b/tests/data/acpi/x86/q35/DSDT.cxl
index 3c34d4dcab16783abe65f6fa5e64eb69d40795fb..0f1ccdfcc3ffbf151c172015cc4bf18bc4ead218 100644
GIT binary patch
delta 180
zcmcbWHaDHiCD<iot}z1xqvJ*{c1b2D=gGp78<-p{CLfjj%kC-V9PI4JG1)*yeDVV+
z4rLB!S1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DMk#%fUBsaw6CN$*GeA
zq#cwNs7#L0XNeDXiVtx1GzbWC4R#Ll4Pz`w?f@B<%21j*`KYv?Q~^WMA}5xqNvQ?R
eV2LD#WakjK$Yd_&$<L+LnS*@8HVevliUR;Q^EU(l
delta 109
zcmV-z0FwWmXWC{8L{mgmS~CCu0c)`e2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvbqc@Dv~7
diff --git a/tests/data/acpi/x86/q35/DSDT.dimmpxm b/tests/data/acpi/x86/q35/DSDT.dimmpxm
index 228374b55bd544116e359f659e546fc66cf8a895..eb5b6e9f52107d9c95e38e94a67a6b5001beafc1 100644
GIT binary patch
delta 173
zcmbQ~cgK&*CD<h-MxB9yQFkMkv?P;v$YgcN4NRV%n{P@gFfw^bP5v#VqRip!>g6NE
z^uK^1xqvZck%QRe6vhIElmf<t0*1r_hSWv=+>_0v{W$n0PEO?dKRI=BhqQyz0+q=z
z`YiFmPVoWGo(2IyuEEYhzF~|7$sHimQW;89C;yf9lPX|HTI9qsH7T{A87z^+kn9}d
W7MaY&JXu~wojJ%iY_q4#1ug)C4>Y*|
delta 141
zcmccPH`9;HCD<iIQk{W;F>NE4v?P;9z+`pF4NPvXn{P@gFfzG|P5v#VB2mDQT)>#J
z$W>@^3S$97N&#a+0Yl;<U!KWM(tgaGlM^S;kajR#XuiO7a*RGpe6Uk|fU~DTK#*&&
ebC7QsqjQK`WHJ|X0V5X4$-kuiHuuS#;{pIXrYYJ0
diff --git a/tests/data/acpi/x86/q35/DSDT.ipmibt b/tests/data/acpi/x86/q35/DSDT.ipmibt
index 45f911ada5645f158f3d6c0c430ec1d52cadc5d8..524fc9f4ee09fd7a5bec62818fd87b6ec300dee8 100644
GIT binary patch
delta 180
zcmaFoxY3ErCD<jzP?3Rw(P1MOyCjp7^JHPk4NMLelaEUNW%rbF4tDnAm~0>;KKX$Z
zhcbt=tCx=u)Bgg7<O0T&MgF3bQy2>vQVJLo3K$X#7*ZGcaZi%=<=~q*Ig#uC<kZOl
z(hf=sR3^vhv&08G#RoWh8UzHn20I7&hA|c-cYq8_WhhOZd{o*`s(>MBkrT_*q|}0D
eutX9=vU7-AWHJ}?<mb}r%t5|kn+0X=vH$?gzc%Cm
delta 109
zcmV-z0FwW)LheBdL{mgm?jQgF0c)`e2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvg;|6`>%)
diff --git a/tests/data/acpi/x86/q35/DSDT.ipmismbus b/tests/data/acpi/x86/q35/DSDT.ipmismbus
index e5d6811bee1233d74236453c49060390d74d4416..d04d215a1d0fbc77739084d100a35af47a1c1a62 100644
GIT binary patch
delta 180
zcmezExX+2pCD<jzPLY9uapOiVc1b2D=gGp78<-p{CLfjj%kC-V9PI4JG1)*yeDVV+
z4rLB!S1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DMk#%fUBsaw6CN$*GeA
zq#cwNs7#L0XNeDXiVtx1GzbWC4R#Ll4Pz`w?f@B<%21j*`KYv?Q~^WMA}5xqNvQ?R
eV2LD#WakjK$Yd_&$<L+LnS*@8HVewUVgUd#3pa@X
delta 109
zcmV-z0FwW{Li<4qL{mgm`yc=S0o<_)2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvhRAPqrav
diff --git a/tests/data/acpi/x86/q35/DSDT.ivrs b/tests/data/acpi/x86/q35/DSDT.ivrs
index 46fd25400b7c00ee9149ddb64cb5d5bd73f6a82b..dbd4f858354df0f4c050fd0b914581154f340ee8 100644
GIT binary patch
delta 180
zcmdnu_}!7qCD<k8y8;6P<Jyf}?2=4Q&Xa{DH!wL^Og<|4m)%p!IoR2cW3qva_~Zvt
z9LgNdu3kPuO#cfQk_#A97Ws=#PGKxyNGV`UC}2n|U`So$$302fmxFKO<V3FjlT#-L
zNINJkP?;Q~&k`T(6d&O1X%G<P8tfe88^&0W+yOEym7z3s@=<9&sRD+iMNTYJlTr(s
e!4gRf$<85ek;z=llb=hgGY9#GZ5EVS%mM(N(>Lb;
delta 109
zcmV-z0FwXrL9{^%L{mgmv>*Tg0oSn#2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRve)OE4?7a
diff --git a/tests/data/acpi/x86/q35/DSDT.memhp b/tests/data/acpi/x86/q35/DSDT.memhp
index 5ce081187a578ba7145a9ba20d30be36c13b7663..f73ade9bf6e4545f9912ed654a282884a54cec79 100644
GIT binary patch
delta 180
zcmez5z14@yCD<jzRE>dw@xewec1b1==gGp78<^ZICLfjj%kC-V9PI4JG1)*yeDVV+
z4rLB!S1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DMk#%fUBsaw6CN$*GeA
zq#cwNs7#L0XNeDXiVtx1GzbWC4R#Ll4Pz`w?f@B<%21j*`KYv?Q~^WMA}5xqNvQ?R
eV2LD#WakjK$Yd_&$<L+LnS*@8HVeu;<OBd!Z#TXG
delta 109
zcmV-z0FwW;O!7+#L{mgm@+ANO0V%Nx2N?oIKa&#~umVFglf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvh0624*0f
diff --git a/tests/data/acpi/x86/q35/DSDT.mmio64 b/tests/data/acpi/x86/q35/DSDT.mmio64
index bdf36c4d575bfc4eb2eac3f00c9b7b4270f88677..f0ddb4c83cdc9afdf4f289a66ed6bf0d630fd623 100644
GIT binary patch
delta 180
zcmeD6y5Pm-66_KZpvu6&xNsvEyCjo`^JHPk4NPtplaEUNW%rbF4tDnAm~0>;KKX$Z
zhcbt=tCx=u)Bgg7<O0T&MgF3bQy2>vQVJLo3K$X#7*ZGcaZi%=<=~q*Ig#uC<kZOl
z(hf=sR3^vhv&08G#RoWh8UzHn20I7&hA|c-cYq8_WhhOZd{o*`s(>MBkrT_*q|}0D
eutX9=vU7-AWHJ}?<mb}r%t5|kn+0Y5Z~y=Y);DGV
delta 109
zcmV-z0FwXEN{vbiL{mgm4J7~o0qL;{2N?oIKa&#~umVFglf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvh{W)LtM&
diff --git a/tests/data/acpi/x86/q35/DSDT.multi-bridge b/tests/data/acpi/x86/q35/DSDT.multi-bridge
index 1db43a69e4c2affd8bd678bbef4d3c228380288e..3ad19e3f5e480db1c449b838c83833f7665186cd 100644
GIT binary patch
delta 180
zcmbP{emkAZCD<k8wlM<(qtZq$c1b2D=gGp78<-p{CLfjj%kC-V9PI4JG1)*yeDVV+
z4rLB!S1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DMk#%fUBsaw6CN$*GeA
zq#cwNs7#L0XNeDXiVtx1GzbWC4R#Ll4Pz`w?f@B<%21j*`KYv?Q~^WMA}5xqNvQ?R
eV2LD#WakjK$Yd_&$<L+LnS*@8HVewMivs{lCO2LH
delta 109
zcmV-z0FwXPXP9RSL{mgmm@@zX0Zg$92N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvd*F{DB}m
diff --git a/tests/data/acpi/x86/q35/DSDT.noacpihp b/tests/data/acpi/x86/q35/DSDT.noacpihp
index 8bc16887e1c963c61aaecf71712a09c0554f6d67..9f7261d1b06bbf5d8a3e5a7a46b247a2a21eb544 100644
GIT binary patch
delta 206
zcmZ4O@XmqDCD<h-Pl17faluBeUE)km&XbRcZ(wq;m|P+8m(x?qIoR2cBU*VfqolCz
z|Nk7$ey-s{O#eBYUA=sSnEn?qBo{EIEb<qfoWfYZkW#>yP{5E_z>vDgk9+cFNnd`x
ziIWq#{!dQj`d`49vb11wptSI0St&K81uBzc^jYGAo#F$WJq-eaT!Wp1e8U(Ek~=^K
zr!thLPOgyhlPX|HTI9qsH7T{A87z^+kn9}d7MaY&Jb9LsI%|+`SZUJacuBF%cclDT
E0gAanng9R*
delta 161
zcmaFou-bvkCD<iITY-Ur@zh4HUE)msc9V~ZZ(#B@o?IdEm(xwmIoR2cBU*VfqolCX
z|Nk7$ey-s{O#cfQk_#A97P$ybPGKxyNGV`UC}2oj<ij(0pQJA{=j6o6!cq>V3(Xgp
yPL9!Mi4S&)4{-K02nccwb`J6lV{{I2i%jNXE?~qWIk{BIZ*sh(*k*ZYe^vm<H!xlR
diff --git a/tests/data/acpi/x86/q35/DSDT.nohpet b/tests/data/acpi/x86/q35/DSDT.nohpet
index c13e45e3612646cc2e30f00b3b7e53335da816ea..c089b5877a0f4d808abd4d8d9396ee7d2a9a78e5 100644
GIT binary patch
delta 191
zcmbR0aKnMiCD<h-LV<yS@!CeNN(m+>=gF-S8<-p{CYwwCW%rbF4tDnAn0!}KT${t$
z&ox|#=|6|FtCx=u)Bgg7<O0T&MgF3bQy2>vQVJLo3K$X#7*ZGcaZfIi^5x*0I60B)
z|K!xkhol^o7N|^)(PxPdc8U*h_B03xat(G4@(p7wNbUfcmda3?I@w&>PpW_+X^|7l
p)TGpcX0SvOL$Y&-TVyg9^W;crb=Dx?u+pT-a#CWOXG>SH008%`I?Dh6
delta 140
zcmV;70CWG?K$SoWL{mgm6(9fr0RXWIc^CpuK9hwQumVjplQ$Xt2Sye{Q$tP&lie8?
zAP7TFMOP96|8M|fZ~<hZL=ux^0dN3hZ~<U&0AZp`43m8tO#=y&VUyAtKp>$vpf!_R
uF9csxLSIlrNia}SMN>mkO;!OzR7P223Img|8x@l@8%~oR8WywO8+rsM6)9){
diff --git a/tests/data/acpi/x86/q35/DSDT.numamem b/tests/data/acpi/x86/q35/DSDT.numamem
index ba6669437e65952f24516ded954b33fe54bdedfb..2867f5b44498d788fc0effd0bf616317821be88e 100644
GIT binary patch
delta 180
zcmZ4K_{NdTCD<k8jRFG$<IIg*?2=3#&Xa{DH!!(bOg<|4m)%p!IoR2cW3qva_~Zvt
z9LgNdu3kPuO#cfQk_#A97Ws=#PGKxyNGV`UC}2n|U`So$$302fmxFKO<V3FjlT#-L
zNINJkP?;Q~&k`T(6d&O1X%G<P8tfe88^&0W+yOEym7z3s@=<9&sRD+iMNTYJlTr(s
e!4gRf$<85ek;z=llb=hgGY9#GZ5EW7!2$q*U^lY>
delta 109
zcmV-z0FwXgL8(CsL{mgmsUQFV0pYO<2N?oIKa&#~umVFglf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRveZD8^j=y
diff --git a/tests/data/acpi/x86/q35/DSDT.pvpanic-isa b/tests/data/acpi/x86/q35/DSDT.pvpanic-isa
index 6ad42873e91c80cef5a42224cb4d31936dad59b4..02cc07f010f880684216ba8925c8f3f55cfd80aa 100644
GIT binary patch
delta 180
zcmeBhI_<>e66_M<t;oQ@xPK!TyCjp7^JHPk4NMLelaEUNW%rbF4tDnAm~0>;KKX$Z
zhcbt=tCx=u)Bgg7<O0T&MgF3bQy2>vQVJLo3K$X#7*ZGcaZi%=<=~q*Ig#uC<kZOl
z(hf=sR3^vhv&08G#RoWh8UzHn20I7&hA|c-cYq8_WhhOZd{o*`s(>MBkrT_*q|}0D
eutX9=vU7-AWHJ}?<mb}r%t5|kn+0XQvj715x;IP!
delta 109
zcmV-z0FwX9LWn{NL{mgm2q6Ff0qL;{2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvh&N%k3a4
diff --git a/tests/data/acpi/x86/q35/DSDT.thread-count b/tests/data/acpi/x86/q35/DSDT.thread-count
index a24b04cbdbf09383b933a42a2a15182545543a87..41c0832ab5041ff5361598813ec28fe7442b191b 100644
GIT binary patch
delta 168
zcmeyEvL%(vCD<ioixC3@W9vpPc1fm&gvr8^8<~1THXoC$VrKV}at?O(<CxqaBR)A!
zmP47t+11NOi0OX;LvjIQ$|47`$tjEl3@HVS2?Y#^1q`W+{JAIB$@+2dO`M#_^?!2e
z<nyu)%nMW|Pd1bj=3y*I?f~geWhhOZ>>}qURltz6$cbfYQffgnSR#ob**U~5GMS5c
Ra+;hvbC7S?<_U5Sg#j0XG*JKm
delta 134
zcmV;10D1qkW$|PRL{mgmaWVh^0k5$N2N?p5TayzRu>y)vv&I>E0|!SILsLUe2$O&u
z7n5Ec2pDhxV{idvqD2yuWC3shWN-msZ~$SVO$?KX9ZmxYlVOwJ9Y6%3H=s3>As!VR
oLsUjtV+sRs0bDNxUsFO~P(w*DP*O!xLsCsvlR+L%v(+Bo6Qh?Xg#Z8m
diff --git a/tests/data/acpi/x86/q35/DSDT.thread-count2 b/tests/data/acpi/x86/q35/DSDT.thread-count2
index 3a0cb8c581c8cc630a2ec21712b7f8b75fcad1c8..153b45f0f7443d25cecc2a752fb6dbd921160e78 100644
GIT binary patch
delta 160
zcmaFW&a}3JiOVI}B}BJ{fr0VbMlN<qrq1%o!jc=A+Hy7@lT_nn@|K$XPEAFL!`ao#
zM~LZv0Yh>DW6B~&vB@cn1q>+#j0pt{i3JR)iyS6vst0iJO`M#_^?!2e<QjDcrUfdK
z52%ZB7bJIpG^a9@rcVB-?k7{gkhI8&WolAtK{Hq)i6PlJ#4R$Ji@6|q@;WtD<{;m&
J&9)kAqXG4WGspk{
delta 142
zcmZ46!St$~iOVI}CFE5z0|O)DMlN<qrnchA!jc=Anlm;ZlT_nn@(`Q+PEAF;fFZen
zF=dgP(Bu@x0)~_V#)JZf#6^CSP1FOJIVUGh?ooFzU1+|*baIS7OMI|Xe1Nm3K|qje
fuyc@a7^8EDTVyg9a{(h3$;t23{Wdpgtd0f%C_O9p
diff --git a/tests/data/acpi/x86/q35/DSDT.tis.tpm12 b/tests/data/acpi/x86/q35/DSDT.tis.tpm12
index e381ce4cbf2b11f56a2d0537db4d21acc97450c9..d0330d26a54b89c02a17b06ef5f55c72e28e406e 100644
GIT binary patch
delta 180
zcmZp4JL1OW66_M<qRha+XuFY%U6RSkd9twN1||oK$wwvsvU^H72Rr+5Og4}apZq|I
zLz%<b)yqeS>3;!3asgw?B7f1zDU1aSDFuuP1q_J=45^F!xF<>ba_~)@oXGWma_Zy&
zX$PeRDwAXMS>l78;scyL4FZB(gPntX!x#&aJ3xk|GL)uHJ}T`eRltz6$cbfYQffgn
dSR#ob**U~5GMS5c@^fi*<{;m&&4Mx?*Z`l;Ho5=+
delta 109
zcmV-z0FwX2MuA2OL{mgm0V4na0cWua2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvhjImmMFN
diff --git a/tests/data/acpi/x86/q35/DSDT.tis.tpm2 b/tests/data/acpi/x86/q35/DSDT.tis.tpm2
index a09253042ce4a715922027245de8a2ab7449c5b7..b05563deedc65df50f35b2399862d9ee8d4d1e0e 100644
GIT binary patch
delta 180
zcmbR3cF&E=CD<h-PMLv$@%u(Dc1b2D=gGp78<-p{CLfjj%kC-V9PI4JG1)*yeDVV+
z4rLB!S1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DMk#%fUBsaw6CN$*GeA
zq#cwNs7#L0XNeDXiVtx1GzbWC4R#Ll4Pz`w?f@B<%21j*`KYv?Q~^WMA}5xqNvQ?R
eV2LD#WakjK$Yd_&$<L+LnS*@8HVevdu>$~1X*S&e
delta 109
zcmV-z0FwXSMw><oL{mgm8zTS!0U@yp2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvZWin{Xbx
diff --git a/tests/data/acpi/x86/q35/DSDT.type4-count b/tests/data/acpi/x86/q35/DSDT.type4-count
index edc23198cdb47a981bcbc82bc8e392b815abb554..00807e7fd4d758bc2ab9c69ac8869cf6864399f7 100644
GIT binary patch
delta 200
zcmbO`k@3MqMlP3Nmyib@3=E8mHgd5`GW8sqEG)T^sdM}0W0I5D*uA8jgPr|2CNnCC
zYjZgJxrPfd{pWCY_3{y7`d`41T)>#J$U$s!3S$97N&#a+0YhQ|L+T=b?#a^>{5bd~
zPEO?dKRI>sa|H*b1uBzc^jYGAo#F$WJq-eaT!Wp1e8U(Ek~=`Ar81PJPL5IZlPX|H
zTI9qsH7T{A87z^+kn9}d7MaY&Jb9sl*knBgLG~cuu+pSx^~s3}!khOi-cthrpxZw^
delta 163
zcmaDbk#X)sMlP3Nmyo$03=E97H*&E{GIj2oEG)T^scrM-W0I5D*xkjPgPr|2CNnCC
zD{wgbxrPfd{V!lhE?`Vq<SH~dg|UDkrGPP^fFW^_FVEzK3VzI-lM^R@S8y<0XuiO7
za*RGpe6Uk|fU~DTK#*&&bC7QsqjQK`WHJ|X0V5X4$&reFOwsC-6BUFvGb!Cu0{{}w
BF&_W`
diff --git a/tests/data/acpi/x86/q35/DSDT.viot b/tests/data/acpi/x86/q35/DSDT.viot
index 4c93dfd5c4b362714d3f9aa606a838d4625b3369..c3d83e67660ee3fd59f6fae6242270bed4a567f1 100644
GIT binary patch
delta 180
zcmbPIbiIhnCD<h-+>(KT@%~0Gc1b2D=gGp78<-p{CLfjj%kC-V9PI4JG1)*yeDVV+
z4rLB!S1%tSrvC*D$pwrli~L0=r!W>Uq!chF6fh(fFr+T><DMk#%fUBsaw6CN$*GeA
zq#cwNs7#L0XNeDXiVtx1GzbWC4R#Ll4Pz`w?f@B<%21j*`KYv?Q~^WMA}5xqNvQ?R
eV2LD#WakjK$Yd_&$<L+LnS*@8HVeuy%K`v;Ha9H*
delta 109
zcmV-z0FwXLa+GokL{mgm6gdC@0SU1R2N?oSK9ds}umVjplf@bR0!9{-#2O?RZ~$X)
z0c4^?5|d;BZ~$a*0bp<dVWLb7lM5S70|}F1lVBS_1)(>fHItJ;91{ouLsUjtV+sS4
PKO7a4!W&MrRvZBxw>BRO
diff --git a/tests/data/acpi/x86/q35/DSDT.xapic b/tests/data/acpi/x86/q35/DSDT.xapic
index d4acd851c62c956436a436f9fa6d08fc5f370fa7..227d421f16ed1824a87e8a91da734828f8b48cbf 100644
GIT binary patch
delta 195
zcmZph&UA7*6PHV{OUTJ?1_s7U8@bpenOZ+i7M9$|)bwogG091M?A}t&!OnghlNmL{
zwK$ypT*HN!{&P6Hdie-3{V!lhE?`Vq<R~^dg|UDkrGPP^fFZGfA$5_%<f$3~9DEZe
zCvyFtoI3f1hJ(@qmB}&sEb+lk@d3`B1_42?!OlUxVT=XI9U#L}8A?+p$7=dX6)+?%
ta$=d9lv>aXmPleqb`EiiOy**qT(7Cl9^@NVniQ=*IZ;D+^8w9ci2(KZKNSD~
delta 162
zcmX>(ovCd)6PHV{OGsNc0|VpRja=-KOigbm3rlWf>VLTTnB*irb`LS<U}ry$$&4D}
z@*K{7uHiyV{|gwB3m8)txd}~9VJu)sDPT+}U`Sl#H+g|Z05j+0#K}K2984FQFEE`P
zqt6l_>=Ym1>}e1X<QnW8<QvB59O4$4%*9;5h(&U8l%^k3wEE;k4dKnqTE`LrM+q_U
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (4 preceding siblings ...)
2025-01-15 18:08 ` [PULL 05/48] tests: acpi: update expected blobs Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 07/48] intel_iommu: Make pasid entry type check accurate Michael S. Tsirkin
` (44 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Yu Zhang, Zhenzhong Duan,
Clément Mathieu--Drif, Yi Liu, Jason Wang, Marcel Apfelbaum,
Paolo Bonzini, Richard Henderson, Eduardo Habkost
From: Yu Zhang <yu.c.zhang@linux.intel.com>
Spec revision 3.0 or above defines more detailed fault reasons for
scalable mode. So introduce them into emulation code, see spec
section 7.1.2 for details.
Note spec revision has no relation with VERSION register, Guest
kernel should not use that register to judge what features are
supported. Instead cap/ecap bits should be checked.
Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-2-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 9 ++++++++-
hw/i386/intel_iommu.c | 25 ++++++++++++++++---------
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 4323fc5d6d..a987023692 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -311,7 +311,14 @@ typedef enum VTDFaultReason {
* request while disabled */
VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */
- VTD_FR_PASID_TABLE_INV = 0x58, /*Invalid PASID table entry */
+ /* PASID directory entry access failure */
+ VTD_FR_PASID_DIR_ACCESS_ERR = 0x50,
+ /* The Present(P) field of pasid directory entry is 0 */
+ VTD_FR_PASID_DIR_ENTRY_P = 0x51,
+ VTD_FR_PASID_TABLE_ACCESS_ERR = 0x58, /* PASID table entry access failure */
+ /* The Present(P) field of pasid table entry is 0 */
+ VTD_FR_PASID_ENTRY_P = 0x59,
+ VTD_FR_PASID_TABLE_ENTRY_INV = 0x5b, /*Invalid PASID table entry */
/* Output address in the interrupt address range for scalable mode */
VTD_FR_SM_INTERRUPT_ADDR = 0x87,
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a8c275f9ce..0ab1676d5f 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -796,7 +796,7 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,
addr = pasid_dir_base + index * entry_size;
if (dma_memory_read(&address_space_memory, addr,
pdire, entry_size, MEMTXATTRS_UNSPECIFIED)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_DIR_ACCESS_ERR;
}
pdire->val = le64_to_cpu(pdire->val);
@@ -814,6 +814,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
dma_addr_t addr,
VTDPASIDEntry *pe)
{
+ uint8_t pgtt;
uint32_t index;
dma_addr_t entry_size;
X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
@@ -823,7 +824,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
addr = addr + index * entry_size;
if (dma_memory_read(&address_space_memory, addr,
pe, entry_size, MEMTXATTRS_UNSPECIFIED)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_TABLE_ACCESS_ERR;
}
for (size_t i = 0; i < ARRAY_SIZE(pe->val); i++) {
pe->val[i] = le64_to_cpu(pe->val[i]);
@@ -831,11 +832,13 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
/* Do translation type check */
if (!vtd_pe_type_check(x86_iommu, pe)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_TABLE_ENTRY_INV;
}
- if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) {
- return -VTD_FR_PASID_TABLE_INV;
+ pgtt = VTD_PE_GET_TYPE(pe);
+ if (pgtt == VTD_SM_PASID_ENTRY_SLT &&
+ !vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) {
+ return -VTD_FR_PASID_TABLE_ENTRY_INV;
}
return 0;
@@ -876,7 +879,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,
}
if (!vtd_pdire_present(&pdire)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_DIR_ENTRY_P;
}
ret = vtd_get_pe_from_pdire(s, pasid, &pdire, pe);
@@ -885,7 +888,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,
}
if (!vtd_pe_present(pe)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_ENTRY_P;
}
return 0;
@@ -938,7 +941,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s,
}
if (!vtd_pdire_present(&pdire)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_DIR_ENTRY_P;
}
/*
@@ -1795,7 +1798,11 @@ static const bool vtd_qualified_faults[] = {
[VTD_FR_ROOT_ENTRY_RSVD] = false,
[VTD_FR_PAGING_ENTRY_RSVD] = true,
[VTD_FR_CONTEXT_ENTRY_TT] = true,
- [VTD_FR_PASID_TABLE_INV] = false,
+ [VTD_FR_PASID_DIR_ACCESS_ERR] = false,
+ [VTD_FR_PASID_DIR_ENTRY_P] = true,
+ [VTD_FR_PASID_TABLE_ACCESS_ERR] = false,
+ [VTD_FR_PASID_ENTRY_P] = true,
+ [VTD_FR_PASID_TABLE_ENTRY_INV] = true,
[VTD_FR_SM_INTERRUPT_ADDR] = true,
[VTD_FR_MAX] = false,
};
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 07/48] intel_iommu: Make pasid entry type check accurate
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (5 preceding siblings ...)
2025-01-15 18:08 ` [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation Michael S. Tsirkin
` (43 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Yi Liu, Clément Mathieu--Drif,
Jason Wang, Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
When guest configures Nested Translation(011b) or First-stage Translation only
(001b), type check passed unaccurately.
Fails the type check in those cases as their simulation isn't supported yet.
Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation")
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-3-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 0ab1676d5f..bd639b7ff7 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -759,20 +759,16 @@ static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu,
VTDPASIDEntry *pe)
{
switch (VTD_PE_GET_TYPE(pe)) {
- case VTD_SM_PASID_ENTRY_FLT:
case VTD_SM_PASID_ENTRY_SLT:
- case VTD_SM_PASID_ENTRY_NESTED:
- break;
+ return true;
case VTD_SM_PASID_ENTRY_PT:
- if (!x86_iommu->pt_supported) {
- return false;
- }
- break;
+ return x86_iommu->pt_supported;
+ case VTD_SM_PASID_ENTRY_FLT:
+ case VTD_SM_PASID_ENTRY_NESTED:
default:
/* Unknown type */
return false;
}
- return true;
}
static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (6 preceding siblings ...)
2025-01-15 18:08 ` [PULL 07/48] intel_iommu: Make pasid entry type check accurate Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Michael S. Tsirkin
` (42 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Yi Liu, Jason Wang,
Clément Mathieu--Drif, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Add an new element flts in IntelIOMMUState to mark stage-1 translation support
in scalable mode, this element will be exposed as an intel_iommu property
x-flts finally.
For now, it's only a placehholder and used for address width compatibility
check and block host device passthrough until nesting is supported.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-4-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 23 ++++++++++++++++++-----
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index d372cd396b..b19f3004f0 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -262,6 +262,7 @@ struct IntelIOMMUState {
bool caching_mode; /* RO - is cap CM enabled? */
bool scalable_mode; /* RO - is Scalable Mode supported? */
+ bool flts; /* RO - is stage-1 translation supported? */
bool snoop_control; /* RO - is SNP filed supported? */
dma_addr_t root; /* Current root table pointer */
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index bd639b7ff7..d0c1d73974 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3917,7 +3917,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod,
return false;
}
- return true;
+ if (!s->flts) {
+ /* All checks requested by VTD stage-2 translation pass */
+ return true;
+ }
+
+ error_setg(errp, "host device is uncompatible with stage-1 translation");
+ return false;
}
static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,
@@ -4307,14 +4313,21 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
}
}
- /* Currently only address widths supported are 39 and 48 bits */
- if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
- (s->aw_bits != VTD_HOST_AW_48BIT)) {
- error_setg(errp, "Supported values for aw-bits are: %d, %d",
+ if (!s->flts && s->aw_bits != VTD_HOST_AW_39BIT &&
+ s->aw_bits != VTD_HOST_AW_48BIT) {
+ error_setg(errp, "%s: supported values for aw-bits are: %d, %d",
+ s->scalable_mode ? "Scalable mode(flts=off)" : "Legacy mode",
VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT);
return false;
}
+ if (s->flts && s->aw_bits != VTD_HOST_AW_48BIT) {
+ error_setg(errp,
+ "Scalable mode(flts=on): supported value for aw-bits is: %d",
+ VTD_HOST_AW_48BIT);
+ return false;
+ }
+
if (s->scalable_mode && !s->dma_drain) {
error_setg(errp, "Need to set dma_drain for scalable mode");
return false;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (7 preceding siblings ...)
2025-01-15 18:08 ` [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 10/48] intel_iommu: Rename slpte to pte Michael S. Tsirkin
` (41 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Clément Mathieu--Drif,
Jason Wang, Yi Liu, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Per VT-d spec 4.1, 6.5.2.4, "Table 21. PASID-based-IOTLB Invalidation",
PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb
entries with matching domain id and pasid.
With stage-1 translation introduced, guest could send PASID-selective
PASID-based iotlb invalidation to flush either stage-1 or stage-2 entries.
By this chance, remove old IOTLB related definitions which were unused.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-5-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 14 ++++--
hw/i386/intel_iommu.c | 85 +++++++++++++++++++++++++++++++++-
2 files changed, 93 insertions(+), 6 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index a987023692..48019e2005 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -404,11 +404,6 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL)
#define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000f100ULL
#define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL
-#define VTD_INV_DESC_IOTLB_PASID_PASID (2ULL << 4)
-#define VTD_INV_DESC_IOTLB_PASID_PAGE (3ULL << 4)
-#define VTD_INV_DESC_IOTLB_PASID(val) (((val) >> 32) & VTD_PASID_ID_MASK)
-#define VTD_INV_DESC_IOTLB_PASID_RSVD_LO 0xfff00000000001c0ULL
-#define VTD_INV_DESC_IOTLB_PASID_RSVD_HI 0xf80ULL
/* Mask for Device IOTLB Invalidate Descriptor */
#define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL)
@@ -443,6 +438,15 @@ typedef union VTDInvDesc VTDInvDesc;
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
+/* Masks for PIOTLB Invalidate Descriptor */
+#define VTD_INV_DESC_PIOTLB_G (3ULL << 4)
+#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4)
+#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4)
+#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
+#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL
+#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL
+
/* Information about page-selective IOTLB invalidate */
struct VTDIOTLBPageInvInfo {
uint16_t domain_id;
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index d0c1d73974..bb1f43c4b3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2692,6 +2692,83 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
return true;
}
+static gboolean vtd_hash_remove_by_pasid(gpointer key, gpointer value,
+ gpointer user_data)
+{
+ VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
+ VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
+
+ return ((entry->domain_id == info->domain_id) &&
+ (entry->pasid == info->pasid));
+}
+
+static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
+ uint16_t domain_id, uint32_t pasid)
+{
+ VTDIOTLBPageInvInfo info;
+ VTDAddressSpace *vtd_as;
+ VTDContextEntry ce;
+
+ info.domain_id = domain_id;
+ info.pasid = pasid;
+
+ vtd_iommu_lock(s);
+ g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid,
+ &info);
+ vtd_iommu_unlock(s);
+
+ QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
+ if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
+ vtd_as->devfn, &ce) &&
+ domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
+ uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce);
+
+ if ((vtd_as->pasid != PCI_NO_PASID || pasid != rid2pasid) &&
+ vtd_as->pasid != pasid) {
+ continue;
+ }
+
+ if (!s->flts) {
+ vtd_address_space_sync(vtd_as);
+ }
+ }
+ }
+}
+
+static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
+ VTDInvDesc *inv_desc)
+{
+ uint16_t domain_id;
+ uint32_t pasid;
+ uint64_t mask[4] = {VTD_INV_DESC_PIOTLB_RSVD_VAL0,
+ VTD_INV_DESC_PIOTLB_RSVD_VAL1,
+ VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE};
+
+ if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, true,
+ __func__, "piotlb inv")) {
+ return false;
+ }
+
+ domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]);
+ pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]);
+ switch (inv_desc->val[0] & VTD_INV_DESC_PIOTLB_G) {
+ case VTD_INV_DESC_PIOTLB_ALL_IN_PASID:
+ vtd_piotlb_pasid_invalidate(s, domain_id, pasid);
+ break;
+
+ case VTD_INV_DESC_PIOTLB_PSI_IN_PASID:
+ break;
+
+ default:
+ error_report_once("%s: invalid piotlb inv desc: hi=0x%"PRIx64
+ ", lo=0x%"PRIx64" (type mismatch: 0x%llx)",
+ __func__, inv_desc->val[1], inv_desc->val[0],
+ inv_desc->val[0] & VTD_INV_DESC_IOTLB_G);
+ return false;
+ }
+ return true;
+}
+
static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -2810,6 +2887,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
}
break;
+ case VTD_INV_DESC_PIOTLB:
+ trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]);
+ if (!vtd_process_piotlb_desc(s, &inv_desc)) {
+ return false;
+ }
+ break;
+
case VTD_INV_DESC_WAIT:
trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
if (!vtd_process_wait_desc(s, &inv_desc)) {
@@ -2837,7 +2921,6 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
* iommu driver) work, just return true is enough so far.
*/
case VTD_INV_DESC_PC:
- case VTD_INV_DESC_PIOTLB:
if (s->scalable_mode) {
break;
}
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 10/48] intel_iommu: Rename slpte to pte
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (8 preceding siblings ...)
2025-01-15 18:08 ` [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Michael S. Tsirkin
@ 2025-01-15 18:08 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 11/48] intel_iommu: Implement stage-1 translation Michael S. Tsirkin
` (40 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:08 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Yi Liu, Clément Mathieu--Drif, Yi Sun,
Zhenzhong Duan, Jason Wang, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Yi Liu <yi.l.liu@intel.com>
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation,
rename variable and functions from slpte to pte whenever possible.
But some are SST only, they are renamed with sl_ prefix.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Co-developed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-6-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 24 +++---
include/hw/i386/intel_iommu.h | 2 +-
hw/i386/intel_iommu.c | 129 +++++++++++++++++----------------
3 files changed, 78 insertions(+), 77 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 48019e2005..e810b0071f 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -533,24 +533,24 @@ typedef struct VTDRootEntry VTDRootEntry;
/* Second Level Page Translation Pointer*/
#define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL)
-/* Paging Structure common */
-#define VTD_SL_PT_PAGE_SIZE_MASK (1ULL << 7)
-/* Bits to decide the offset for each level */
-#define VTD_SL_LEVEL_BITS 9
-
/* Second Level Paging Structure */
-#define VTD_SL_PML4_LEVEL 4
-#define VTD_SL_PDP_LEVEL 3
-#define VTD_SL_PD_LEVEL 2
-#define VTD_SL_PT_LEVEL 1
-#define VTD_SL_PT_ENTRY_NR 512
-
/* Masks for Second Level Paging Entry */
#define VTD_SL_RW_MASK 3ULL
#define VTD_SL_R 1ULL
#define VTD_SL_W (1ULL << 1)
-#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
#define VTD_SL_IGN_COM 0xbff0000000000000ULL
#define VTD_SL_TM (1ULL << 62)
+/* Common for both First Level and Second Level */
+#define VTD_PML4_LEVEL 4
+#define VTD_PDP_LEVEL 3
+#define VTD_PD_LEVEL 2
+#define VTD_PT_LEVEL 1
+#define VTD_PT_ENTRY_NR 512
+#define VTD_PT_PAGE_SIZE_MASK (1ULL << 7)
+#define VTD_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
+
+/* Bits to decide the offset for each level */
+#define VTD_LEVEL_BITS 9
+
#endif
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index b19f3004f0..f44f3eb63a 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -152,7 +152,7 @@ struct VTDIOTLBEntry {
uint64_t gfn;
uint16_t domain_id;
uint32_t pasid;
- uint64_t slpte;
+ uint64_t pte;
uint64_t mask;
uint8_t access_flags;
};
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index bb1f43c4b3..dfac5982d6 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -48,7 +48,8 @@
/* pe operations */
#define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
-#define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW))
+#define VTD_PE_GET_SL_LEVEL(pe) \
+ (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW))
/*
* PCI bus number (or SID) is not reliable since the device is usaully
@@ -284,15 +285,15 @@ static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
}
/* The shift of an addr for a certain level of paging structure */
-static inline uint32_t vtd_slpt_level_shift(uint32_t level)
+static inline uint32_t vtd_pt_level_shift(uint32_t level)
{
assert(level != 0);
- return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
+ return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_LEVEL_BITS;
}
-static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
+static inline uint64_t vtd_pt_level_page_mask(uint32_t level)
{
- return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
+ return ~((1ULL << vtd_pt_level_shift(level)) - 1);
}
static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
@@ -349,7 +350,7 @@ static void vtd_reset_caches(IntelIOMMUState *s)
static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
{
- return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
+ return (addr & vtd_pt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
}
/* Must be called with IOMMU lock held */
@@ -360,7 +361,7 @@ static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
VTDIOTLBEntry *entry;
unsigned level;
- for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
+ for (level = VTD_PT_LEVEL; level < VTD_PML4_LEVEL; level++) {
key.gfn = vtd_get_iotlb_gfn(addr, level);
key.level = level;
key.sid = source_id;
@@ -377,7 +378,7 @@ out:
/* Must be with IOMMU lock held */
static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
- uint16_t domain_id, hwaddr addr, uint64_t slpte,
+ uint16_t domain_id, hwaddr addr, uint64_t pte,
uint8_t access_flags, uint32_t level,
uint32_t pasid)
{
@@ -385,7 +386,7 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
struct vtd_iotlb_key *key = g_malloc(sizeof(*key));
uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
- trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);
+ trace_vtd_iotlb_page_update(source_id, addr, pte, domain_id);
if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
trace_vtd_iotlb_reset("iotlb exceeds size limit");
vtd_reset_iotlb_locked(s);
@@ -393,9 +394,9 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
entry->gfn = gfn;
entry->domain_id = domain_id;
- entry->slpte = slpte;
+ entry->pte = pte;
entry->access_flags = access_flags;
- entry->mask = vtd_slpt_level_page_mask(level);
+ entry->mask = vtd_pt_level_page_mask(level);
entry->pasid = pasid;
key->gfn = gfn;
@@ -710,32 +711,32 @@ static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce)
return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
}
-static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw)
+static inline uint64_t vtd_get_pte_addr(uint64_t pte, uint8_t aw)
{
- return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw);
+ return pte & VTD_PT_BASE_ADDR_MASK(aw);
}
/* Whether the pte indicates the address of the page frame */
-static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
+static inline bool vtd_is_last_pte(uint64_t pte, uint32_t level)
{
- return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
+ return level == VTD_PT_LEVEL || (pte & VTD_PT_PAGE_SIZE_MASK);
}
-/* Get the content of a spte located in @base_addr[@index] */
-static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
+/* Get the content of a pte located in @base_addr[@index] */
+static uint64_t vtd_get_pte(dma_addr_t base_addr, uint32_t index)
{
- uint64_t slpte;
+ uint64_t pte;
- assert(index < VTD_SL_PT_ENTRY_NR);
+ assert(index < VTD_PT_ENTRY_NR);
if (dma_memory_read(&address_space_memory,
- base_addr + index * sizeof(slpte),
- &slpte, sizeof(slpte), MEMTXATTRS_UNSPECIFIED)) {
- slpte = (uint64_t)-1;
- return slpte;
+ base_addr + index * sizeof(pte),
+ &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) {
+ pte = (uint64_t)-1;
+ return pte;
}
- slpte = le64_to_cpu(slpte);
- return slpte;
+ pte = le64_to_cpu(pte);
+ return pte;
}
/* Given an iova and the level of paging structure, return the offset
@@ -743,12 +744,12 @@ static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
*/
static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level)
{
- return (iova >> vtd_slpt_level_shift(level)) &
- ((1ULL << VTD_SL_LEVEL_BITS) - 1);
+ return (iova >> vtd_pt_level_shift(level)) &
+ ((1ULL << VTD_LEVEL_BITS) - 1);
}
/* Check Capability Register to see if the @level of page-table is supported */
-static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
+static inline bool vtd_is_sl_level_supported(IntelIOMMUState *s, uint32_t level)
{
return VTD_CAP_SAGAW_MASK & s->cap &
(1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
@@ -833,7 +834,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
pgtt = VTD_PE_GET_TYPE(pe);
if (pgtt == VTD_SM_PASID_ENTRY_SLT &&
- !vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) {
+ !vtd_is_sl_level_supported(s, VTD_PE_GET_SL_LEVEL(pe))) {
return -VTD_FR_PASID_TABLE_ENTRY_INV;
}
@@ -972,7 +973,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s,
if (s->root_scalable) {
vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid);
- return VTD_PE_GET_LEVEL(&pe);
+ return VTD_PE_GET_SL_LEVEL(&pe);
}
return vtd_ce_get_level(ce);
@@ -1040,9 +1041,9 @@ static inline uint64_t vtd_iova_limit(IntelIOMMUState *s,
}
/* Return true if IOVA passes range check, otherwise false. */
-static inline bool vtd_iova_range_check(IntelIOMMUState *s,
- uint64_t iova, VTDContextEntry *ce,
- uint8_t aw, uint32_t pasid)
+static inline bool vtd_iova_sl_range_check(IntelIOMMUState *s,
+ uint64_t iova, VTDContextEntry *ce,
+ uint8_t aw, uint32_t pasid)
{
/*
* Check if @iova is above 2^X-1, where X is the minimum of MGAW
@@ -1083,17 +1084,17 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
/*
* We should have caught a guest-mis-programmed level earlier,
- * via vtd_is_level_supported.
+ * via vtd_is_sl_level_supported.
*/
assert(level < VTD_SPTE_RSVD_LEN);
/*
- * Zero level doesn't exist. The smallest level is VTD_SL_PT_LEVEL=1 and
- * checked by vtd_is_last_slpte().
+ * Zero level doesn't exist. The smallest level is VTD_PT_LEVEL=1 and
+ * checked by vtd_is_last_pte().
*/
assert(level);
- if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) &&
- (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) {
+ if ((level == VTD_PD_LEVEL || level == VTD_PDP_LEVEL) &&
+ (slpte & VTD_PT_PAGE_SIZE_MASK)) {
/* large page */
rsvd_mask = vtd_spte_rsvd_large[level];
} else {
@@ -1119,7 +1120,7 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce,
uint64_t access_right_check;
uint64_t xlat, size;
- if (!vtd_iova_range_check(s, iova, ce, aw_bits, pasid)) {
+ if (!vtd_iova_sl_range_check(s, iova, ce, aw_bits, pasid)) {
error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64 ","
"pasid=0x%" PRIx32 ")", __func__, iova, pasid);
return -VTD_FR_ADDR_BEYOND_MGAW;
@@ -1130,7 +1131,7 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce,
while (true) {
offset = vtd_iova_level_offset(iova, level);
- slpte = vtd_get_slpte(addr, offset);
+ slpte = vtd_get_pte(addr, offset);
if (slpte == (uint64_t)-1) {
error_report_once("%s: detected read error on DMAR slpte "
@@ -1161,17 +1162,17 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce,
return -VTD_FR_PAGING_ENTRY_RSVD;
}
- if (vtd_is_last_slpte(slpte, level)) {
+ if (vtd_is_last_pte(slpte, level)) {
*slptep = slpte;
*slpte_level = level;
break;
}
- addr = vtd_get_slpte_addr(slpte, aw_bits);
+ addr = vtd_get_pte_addr(slpte, aw_bits);
level--;
}
- xlat = vtd_get_slpte_addr(*slptep, aw_bits);
- size = ~vtd_slpt_level_page_mask(level) + 1;
+ xlat = vtd_get_pte_addr(*slptep, aw_bits);
+ size = ~vtd_pt_level_page_mask(level) + 1;
/*
* From VT-d spec 3.14: Untranslated requests and translation
@@ -1322,14 +1323,14 @@ static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
trace_vtd_page_walk_level(addr, level, start, end);
- subpage_size = 1ULL << vtd_slpt_level_shift(level);
- subpage_mask = vtd_slpt_level_page_mask(level);
+ subpage_size = 1ULL << vtd_pt_level_shift(level);
+ subpage_mask = vtd_pt_level_page_mask(level);
while (iova < end) {
iova_next = (iova & subpage_mask) + subpage_size;
offset = vtd_iova_level_offset(iova, level);
- slpte = vtd_get_slpte(addr, offset);
+ slpte = vtd_get_pte(addr, offset);
if (slpte == (uint64_t)-1) {
trace_vtd_page_walk_skip_read(iova, iova_next);
@@ -1352,12 +1353,12 @@ static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
*/
entry_valid = read_cur | write_cur;
- if (!vtd_is_last_slpte(slpte, level) && entry_valid) {
+ if (!vtd_is_last_pte(slpte, level) && entry_valid) {
/*
* This is a valid PDE (or even bigger than PDE). We need
* to walk one further level.
*/
- ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw),
+ ret = vtd_page_walk_level(vtd_get_pte_addr(slpte, info->aw),
iova, MIN(iova_next, end), level - 1,
read_cur, write_cur, info);
} else {
@@ -1374,7 +1375,7 @@ static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
event.entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
event.entry.addr_mask = ~subpage_mask;
/* NOTE: this is only meaningful if entry_valid == true */
- event.entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw);
+ event.entry.translated_addr = vtd_get_pte_addr(slpte, info->aw);
event.type = event.entry.perm ? IOMMU_NOTIFIER_MAP :
IOMMU_NOTIFIER_UNMAP;
ret = vtd_page_walk_one(&event, info);
@@ -1408,11 +1409,11 @@ static int vtd_page_walk(IntelIOMMUState *s, VTDContextEntry *ce,
dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce, pasid);
uint32_t level = vtd_get_iova_level(s, ce, pasid);
- if (!vtd_iova_range_check(s, start, ce, info->aw, pasid)) {
+ if (!vtd_iova_sl_range_check(s, start, ce, info->aw, pasid)) {
return -VTD_FR_ADDR_BEYOND_MGAW;
}
- if (!vtd_iova_range_check(s, end, ce, info->aw, pasid)) {
+ if (!vtd_iova_sl_range_check(s, end, ce, info->aw, pasid)) {
/* Fix end so that it reaches the maximum */
end = vtd_iova_limit(s, ce, info->aw, pasid);
}
@@ -1527,7 +1528,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
/* Check if the programming of context-entry is valid */
if (!s->root_scalable &&
- !vtd_is_level_supported(s, vtd_ce_get_level(ce))) {
+ !vtd_is_sl_level_supported(s, vtd_ce_get_level(ce))) {
error_report_once("%s: invalid context entry: hi=%"PRIx64
", lo=%"PRIx64" (level %d not supported)",
__func__, ce->hi, ce->lo,
@@ -1897,7 +1898,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
VTDContextEntry ce;
uint8_t bus_num = pci_bus_num(bus);
VTDContextCacheEntry *cc_entry;
- uint64_t slpte, page_mask;
+ uint64_t pte, page_mask;
uint32_t level, pasid = vtd_as->pasid;
uint16_t source_id = PCI_BUILD_BDF(bus_num, devfn);
int ret_fr;
@@ -1918,13 +1919,13 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
cc_entry = &vtd_as->context_cache_entry;
- /* Try to fetch slpte form IOTLB, we don't need RID2PASID logic */
+ /* Try to fetch pte from IOTLB, we don't need RID2PASID logic */
if (!rid2pasid) {
iotlb_entry = vtd_lookup_iotlb(s, source_id, pasid, addr);
if (iotlb_entry) {
- trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,
+ trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte,
iotlb_entry->domain_id);
- slpte = iotlb_entry->slpte;
+ pte = iotlb_entry->pte;
access_flags = iotlb_entry->access_flags;
page_mask = iotlb_entry->mask;
goto out;
@@ -1996,20 +1997,20 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
return true;
}
- /* Try to fetch slpte form IOTLB for RID2PASID slow path */
+ /* Try to fetch pte from IOTLB for RID2PASID slow path */
if (rid2pasid) {
iotlb_entry = vtd_lookup_iotlb(s, source_id, pasid, addr);
if (iotlb_entry) {
- trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,
+ trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte,
iotlb_entry->domain_id);
- slpte = iotlb_entry->slpte;
+ pte = iotlb_entry->pte;
access_flags = iotlb_entry->access_flags;
page_mask = iotlb_entry->mask;
goto out;
}
}
- ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level,
+ ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level,
&reads, &writes, s->aw_bits, pasid);
if (ret_fr) {
vtd_report_fault(s, -ret_fr, is_fpd_set, source_id,
@@ -2017,14 +2018,14 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
goto error;
}
- page_mask = vtd_slpt_level_page_mask(level);
+ page_mask = vtd_pt_level_page_mask(level);
access_flags = IOMMU_ACCESS_FLAG(reads, writes);
vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce, pasid),
- addr, slpte, access_flags, level, pasid);
+ addr, pte, access_flags, level, pasid);
out:
vtd_iommu_unlock(s);
entry->iova = addr & page_mask;
- entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask;
+ entry->translated_addr = vtd_get_pte_addr(pte, s->aw_bits) & page_mask;
entry->addr_mask = ~page_mask;
entry->perm = access_flags;
return true;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 11/48] intel_iommu: Implement stage-1 translation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (9 preceding siblings ...)
2025-01-15 18:08 ` [PULL 10/48] intel_iommu: Rename slpte to pte Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 12/48] intel_iommu: Check if the input address is canonical Michael S. Tsirkin
` (39 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Yi Liu, Clément Mathieu--Drif, Yi Sun,
Zhenzhong Duan, Jason Wang, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Yi Liu <yi.l.liu@intel.com>
This adds stage-1 page table walking to support stage-1 only
translation in scalable mode.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Co-developed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-7-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 34 +++++++
hw/i386/intel_iommu.c | 158 ++++++++++++++++++++++++++++++++-
2 files changed, 188 insertions(+), 4 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index e810b0071f..86d3354198 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -320,6 +320,15 @@ typedef enum VTDFaultReason {
VTD_FR_PASID_ENTRY_P = 0x59,
VTD_FR_PASID_TABLE_ENTRY_INV = 0x5b, /*Invalid PASID table entry */
+ /* Fail to access a first-level paging entry (not FS_PML4E) */
+ VTD_FR_FS_PAGING_ENTRY_INV = 0x70,
+ VTD_FR_FS_PAGING_ENTRY_P = 0x71,
+ /* Non-zero reserved field in present first-stage paging entry */
+ VTD_FR_FS_PAGING_ENTRY_RSVD = 0x72,
+ VTD_FR_PASID_ENTRY_FSPTPTR_INV = 0x73, /* Invalid FSPTPTR in PASID entry */
+ VTD_FR_FS_PAGING_ENTRY_US = 0x81, /* Privilege violation */
+ VTD_FR_SM_WRITE = 0x85, /* No write permission */
+
/* Output address in the interrupt address range for scalable mode */
VTD_FR_SM_INTERRUPT_ADDR = 0x87,
VTD_FR_MAX, /* Guard */
@@ -438,6 +447,22 @@ typedef union VTDInvDesc VTDInvDesc;
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
+/* Rsvd field masks for fpte */
+#define VTD_FS_UPPER_IGNORED 0xfff0000000000000ULL
+#define VTD_FPTE_PAGE_L1_RSVD_MASK(aw) \
+ (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
+#define VTD_FPTE_PAGE_L2_RSVD_MASK(aw) \
+ (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
+#define VTD_FPTE_PAGE_L3_RSVD_MASK(aw) \
+ (~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
+#define VTD_FPTE_PAGE_L4_RSVD_MASK(aw) \
+ (0x80ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
+
+#define VTD_FPTE_LPAGE_L2_RSVD_MASK(aw) \
+ (0x1fe000ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
+#define VTD_FPTE_LPAGE_L3_RSVD_MASK(aw) \
+ (0x3fffe000ULL | ~(VTD_HAW_MASK(aw) | VTD_FS_UPPER_IGNORED))
+
/* Masks for PIOTLB Invalidate Descriptor */
#define VTD_INV_DESC_PIOTLB_G (3ULL << 4)
#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4)
@@ -530,6 +555,15 @@ typedef struct VTDRootEntry VTDRootEntry;
#define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-width */
#define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK)
+#define VTD_SM_PASID_ENTRY_FLPM 3ULL
+#define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL)
+
+/* First Level Paging Structure */
+/* Masks for First Level Paging Entry */
+#define VTD_FL_P 1ULL
+#define VTD_FL_RW (1ULL << 1)
+#define VTD_FL_US (1ULL << 2)
+
/* Second Level Page Translation Pointer*/
#define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index dfac5982d6..bd6de71c02 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -48,6 +48,8 @@
/* pe operations */
#define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
+#define VTD_PE_GET_FL_LEVEL(pe) \
+ (4 + (((pe)->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM))
#define VTD_PE_GET_SL_LEVEL(pe) \
(2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW))
@@ -755,6 +757,11 @@ static inline bool vtd_is_sl_level_supported(IntelIOMMUState *s, uint32_t level)
(1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
}
+static inline bool vtd_is_fl_level_supported(IntelIOMMUState *s, uint32_t level)
+{
+ return level == VTD_PML4_LEVEL;
+}
+
/* Return true if check passed, otherwise false */
static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu,
VTDPASIDEntry *pe)
@@ -838,6 +845,11 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
return -VTD_FR_PASID_TABLE_ENTRY_INV;
}
+ if (pgtt == VTD_SM_PASID_ENTRY_FLT &&
+ !vtd_is_fl_level_supported(s, VTD_PE_GET_FL_LEVEL(pe))) {
+ return -VTD_FR_PASID_TABLE_ENTRY_INV;
+ }
+
return 0;
}
@@ -973,7 +985,11 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s,
if (s->root_scalable) {
vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid);
- return VTD_PE_GET_SL_LEVEL(&pe);
+ if (s->flts) {
+ return VTD_PE_GET_FL_LEVEL(&pe);
+ } else {
+ return VTD_PE_GET_SL_LEVEL(&pe);
+ }
}
return vtd_ce_get_level(ce);
@@ -1060,7 +1076,11 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
if (s->root_scalable) {
vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid);
- return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR;
+ if (s->flts) {
+ return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR;
+ } else {
+ return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR;
+ }
}
return vtd_ce_get_slpt_base(ce);
@@ -1800,6 +1820,12 @@ static const bool vtd_qualified_faults[] = {
[VTD_FR_PASID_TABLE_ACCESS_ERR] = false,
[VTD_FR_PASID_ENTRY_P] = true,
[VTD_FR_PASID_TABLE_ENTRY_INV] = true,
+ [VTD_FR_FS_PAGING_ENTRY_INV] = true,
+ [VTD_FR_FS_PAGING_ENTRY_P] = true,
+ [VTD_FR_FS_PAGING_ENTRY_RSVD] = true,
+ [VTD_FR_PASID_ENTRY_FSPTPTR_INV] = true,
+ [VTD_FR_FS_PAGING_ENTRY_US] = true,
+ [VTD_FR_SM_WRITE] = true,
[VTD_FR_SM_INTERRUPT_ADDR] = true,
[VTD_FR_MAX] = false,
};
@@ -1862,6 +1888,113 @@ out:
trace_vtd_pt_enable_fast_path(source_id, success);
}
+/*
+ * Rsvd field masks for fpte:
+ * vtd_fpte_rsvd 4k pages
+ * vtd_fpte_rsvd_large large pages
+ *
+ * We support only 4-level page tables.
+ */
+#define VTD_FPTE_RSVD_LEN 5
+static uint64_t vtd_fpte_rsvd[VTD_FPTE_RSVD_LEN];
+static uint64_t vtd_fpte_rsvd_large[VTD_FPTE_RSVD_LEN];
+
+static bool vtd_flpte_nonzero_rsvd(uint64_t flpte, uint32_t level)
+{
+ uint64_t rsvd_mask;
+
+ /*
+ * We should have caught a guest-mis-programmed level earlier,
+ * via vtd_is_fl_level_supported.
+ */
+ assert(level < VTD_FPTE_RSVD_LEN);
+ /*
+ * Zero level doesn't exist. The smallest level is VTD_PT_LEVEL=1 and
+ * checked by vtd_is_last_pte().
+ */
+ assert(level);
+
+ if ((level == VTD_PD_LEVEL || level == VTD_PDP_LEVEL) &&
+ (flpte & VTD_PT_PAGE_SIZE_MASK)) {
+ /* large page */
+ rsvd_mask = vtd_fpte_rsvd_large[level];
+ } else {
+ rsvd_mask = vtd_fpte_rsvd[level];
+ }
+
+ return flpte & rsvd_mask;
+}
+
+static inline bool vtd_flpte_present(uint64_t flpte)
+{
+ return !!(flpte & VTD_FL_P);
+}
+
+/*
+ * Given the @iova, get relevant @flptep. @flpte_level will be the last level
+ * of the translation, can be used for deciding the size of large page.
+ */
+static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce,
+ uint64_t iova, bool is_write,
+ uint64_t *flptep, uint32_t *flpte_level,
+ bool *reads, bool *writes, uint8_t aw_bits,
+ uint32_t pasid)
+{
+ dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce, pasid);
+ uint32_t level = vtd_get_iova_level(s, ce, pasid);
+ uint32_t offset;
+ uint64_t flpte;
+
+ while (true) {
+ offset = vtd_iova_level_offset(iova, level);
+ flpte = vtd_get_pte(addr, offset);
+
+ if (flpte == (uint64_t)-1) {
+ if (level == vtd_get_iova_level(s, ce, pasid)) {
+ /* Invalid programming of pasid-entry */
+ return -VTD_FR_PASID_ENTRY_FSPTPTR_INV;
+ } else {
+ return -VTD_FR_FS_PAGING_ENTRY_INV;
+ }
+ }
+
+ if (!vtd_flpte_present(flpte)) {
+ *reads = false;
+ *writes = false;
+ return -VTD_FR_FS_PAGING_ENTRY_P;
+ }
+
+ /* No emulated device supports supervisor privilege request yet */
+ if (!(flpte & VTD_FL_US)) {
+ *reads = false;
+ *writes = false;
+ return -VTD_FR_FS_PAGING_ENTRY_US;
+ }
+
+ *reads = true;
+ *writes = (*writes) && (flpte & VTD_FL_RW);
+ if (is_write && !(flpte & VTD_FL_RW)) {
+ return -VTD_FR_SM_WRITE;
+ }
+ if (vtd_flpte_nonzero_rsvd(flpte, level)) {
+ error_report_once("%s: detected flpte reserved non-zero "
+ "iova=0x%" PRIx64 ", level=0x%" PRIx32
+ "flpte=0x%" PRIx64 ", pasid=0x%" PRIX32 ")",
+ __func__, iova, level, flpte, pasid);
+ return -VTD_FR_FS_PAGING_ENTRY_RSVD;
+ }
+
+ if (vtd_is_last_pte(flpte, level)) {
+ *flptep = flpte;
+ *flpte_level = level;
+ return 0;
+ }
+
+ addr = vtd_get_pte_addr(flpte, aw_bits);
+ level--;
+ }
+}
+
static void vtd_report_fault(IntelIOMMUState *s,
int err, bool is_fpd_set,
uint16_t source_id,
@@ -2010,8 +2143,13 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
}
}
- ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level,
- &reads, &writes, s->aw_bits, pasid);
+ if (s->flts && s->root_scalable) {
+ ret_fr = vtd_iova_to_flpte(s, &ce, addr, is_write, &pte, &level,
+ &reads, &writes, s->aw_bits, pasid);
+ } else {
+ ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level,
+ &reads, &writes, s->aw_bits, pasid);
+ }
if (ret_fr) {
vtd_report_fault(s, -ret_fr, is_fpd_set, source_id,
addr, is_write, pasid != PCI_NO_PASID, pasid);
@@ -4286,6 +4424,18 @@ static void vtd_init(IntelIOMMUState *s)
vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
x86_iommu->dt_supported && s->stale_tm);
+ /*
+ * Rsvd field masks for fpte
+ */
+ vtd_fpte_rsvd[0] = ~0ULL;
+ vtd_fpte_rsvd[1] = VTD_FPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_fpte_rsvd[2] = VTD_FPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_fpte_rsvd[3] = VTD_FPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_fpte_rsvd[4] = VTD_FPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
+
+ vtd_fpte_rsvd_large[2] = VTD_FPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_fpte_rsvd_large[3] = VTD_FPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+
if (s->scalable_mode || s->snoop_control) {
vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 12/48] intel_iommu: Check if the input address is canonical
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (10 preceding siblings ...)
2025-01-15 18:09 ` [PULL 11/48] intel_iommu: Implement stage-1 translation Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range Michael S. Tsirkin
` (38 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Clément Mathieu--Drif, Zhenzhong Duan,
Jason Wang, Yi Liu, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Stage-1 translation must fail if the address to translate is
not canonical.
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-8-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 1 +
hw/i386/intel_iommu.c | 23 +++++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 86d3354198..3e7365dfff 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -326,6 +326,7 @@ typedef enum VTDFaultReason {
/* Non-zero reserved field in present first-stage paging entry */
VTD_FR_FS_PAGING_ENTRY_RSVD = 0x72,
VTD_FR_PASID_ENTRY_FSPTPTR_INV = 0x73, /* Invalid FSPTPTR in PASID entry */
+ VTD_FR_FS_NON_CANONICAL = 0x80, /* SNG.1 : Address for FS not canonical.*/
VTD_FR_FS_PAGING_ENTRY_US = 0x81, /* Privilege violation */
VTD_FR_SM_WRITE = 0x85, /* No write permission */
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index bd6de71c02..3959fe44c7 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1824,6 +1824,7 @@ static const bool vtd_qualified_faults[] = {
[VTD_FR_FS_PAGING_ENTRY_P] = true,
[VTD_FR_FS_PAGING_ENTRY_RSVD] = true,
[VTD_FR_PASID_ENTRY_FSPTPTR_INV] = true,
+ [VTD_FR_FS_NON_CANONICAL] = true,
[VTD_FR_FS_PAGING_ENTRY_US] = true,
[VTD_FR_SM_WRITE] = true,
[VTD_FR_SM_INTERRUPT_ADDR] = true,
@@ -1930,6 +1931,22 @@ static inline bool vtd_flpte_present(uint64_t flpte)
return !!(flpte & VTD_FL_P);
}
+/* Return true if IOVA is canonical, otherwise false. */
+static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova,
+ VTDContextEntry *ce, uint32_t pasid)
+{
+ uint64_t iova_limit = vtd_iova_limit(s, ce, s->aw_bits, pasid);
+ uint64_t upper_bits_mask = ~(iova_limit - 1);
+ uint64_t upper_bits = iova & upper_bits_mask;
+ bool msb = ((iova & (iova_limit >> 1)) != 0);
+
+ if (msb) {
+ return upper_bits == upper_bits_mask;
+ } else {
+ return !upper_bits;
+ }
+}
+
/*
* Given the @iova, get relevant @flptep. @flpte_level will be the last level
* of the translation, can be used for deciding the size of large page.
@@ -1945,6 +1962,12 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce,
uint32_t offset;
uint64_t flpte;
+ if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) {
+ error_report_once("%s: detected non canonical IOVA (iova=0x%" PRIx64 ","
+ "pasid=0x%" PRIx32 ")", __func__, iova, pasid);
+ return -VTD_FR_FS_NON_CANONICAL;
+ }
+
while (true) {
offset = vtd_iova_level_offset(iova, level);
flpte = vtd_get_pte(addr, offset);
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (11 preceding siblings ...)
2025-01-15 18:09 ` [PULL 12/48] intel_iommu: Check if the input address is canonical Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation Michael S. Tsirkin
` (37 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Yi Liu, Clément Mathieu--Drif,
Jason Wang, Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Per VT-d spec 4.1 section 3.15, "Untranslated requests and translation
requests that result in an address in the interrupt range will be
blocked with condition code LGN.4 or SGN.8."
This applies to both stage-1 and stage-2 IOMMU page table, move the
check from vtd_iova_to_slpte() to vtd_do_iommu_translate() so stage-1
page table could also be checked.
By this chance, update the comment with correct section number.
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-9-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 48 ++++++++++++++++++++++---------------------
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 3959fe44c7..d53ce01e82 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1138,7 +1138,6 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce,
uint32_t offset;
uint64_t slpte;
uint64_t access_right_check;
- uint64_t xlat, size;
if (!vtd_iova_sl_range_check(s, iova, ce, aw_bits, pasid)) {
error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64 ","
@@ -1191,28 +1190,7 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce,
level--;
}
- xlat = vtd_get_pte_addr(*slptep, aw_bits);
- size = ~vtd_pt_level_page_mask(level) + 1;
-
- /*
- * From VT-d spec 3.14: Untranslated requests and translation
- * requests that result in an address in the interrupt range will be
- * blocked with condition code LGN.4 or SGN.8.
- */
- if ((xlat > VTD_INTERRUPT_ADDR_LAST ||
- xlat + size - 1 < VTD_INTERRUPT_ADDR_FIRST)) {
- return 0;
- } else {
- error_report_once("%s: xlat address is in interrupt range "
- "(iova=0x%" PRIx64 ", level=0x%" PRIx32 ", "
- "slpte=0x%" PRIx64 ", write=%d, "
- "xlat=0x%" PRIx64 ", size=0x%" PRIx64 ", "
- "pasid=0x%" PRIx32 ")",
- __func__, iova, level, slpte, is_write,
- xlat, size, pasid);
- return s->scalable_mode ? -VTD_FR_SM_INTERRUPT_ADDR :
- -VTD_FR_INTERRUPT_ADDR;
- }
+ return 0;
}
typedef int (*vtd_page_walk_hook)(const IOMMUTLBEvent *event, void *private);
@@ -2064,6 +2042,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
uint8_t access_flags;
bool rid2pasid = (pasid == PCI_NO_PASID) && s->root_scalable;
VTDIOTLBEntry *iotlb_entry;
+ uint64_t xlat, size;
/*
* We have standalone memory region for interrupt addresses, we
@@ -2173,6 +2152,29 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level,
&reads, &writes, s->aw_bits, pasid);
}
+ if (!ret_fr) {
+ xlat = vtd_get_pte_addr(pte, s->aw_bits);
+ size = ~vtd_pt_level_page_mask(level) + 1;
+
+ /*
+ * Per VT-d spec 4.1 section 3.15: Untranslated requests and translation
+ * requests that result in an address in the interrupt range will be
+ * blocked with condition code LGN.4 or SGN.8.
+ */
+ if ((xlat <= VTD_INTERRUPT_ADDR_LAST &&
+ xlat + size - 1 >= VTD_INTERRUPT_ADDR_FIRST)) {
+ error_report_once("%s: xlat address is in interrupt range "
+ "(iova=0x%" PRIx64 ", level=0x%" PRIx32 ", "
+ "pte=0x%" PRIx64 ", write=%d, "
+ "xlat=0x%" PRIx64 ", size=0x%" PRIx64 ", "
+ "pasid=0x%" PRIx32 ")",
+ __func__, addr, level, pte, is_write,
+ xlat, size, pasid);
+ ret_fr = s->scalable_mode ? -VTD_FR_SM_INTERRUPT_ADDR :
+ -VTD_FR_INTERRUPT_ADDR;
+ }
+ }
+
if (ret_fr) {
vtd_report_fault(s, -ret_fr, is_fpd_set, source_id,
addr, is_write, pasid != PCI_NO_PASID, pasid);
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (12 preceding siblings ...)
2025-01-15 18:09 ` [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation Michael S. Tsirkin
` (36 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Clément Mathieu--Drif, Zhenzhong Duan, Yi Liu,
Jason Wang, Marcel Apfelbaum, Paolo Bonzini, Richard Henderson,
Eduardo Habkost
From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-10-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 3 +++
hw/i386/intel_iommu.c | 25 ++++++++++++++++++++++++-
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 3e7365dfff..22dd3faf0c 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -332,6 +332,7 @@ typedef enum VTDFaultReason {
/* Output address in the interrupt address range for scalable mode */
VTD_FR_SM_INTERRUPT_ADDR = 0x87,
+ VTD_FR_FS_BIT_UPDATE_FAILED = 0x91, /* SFS.10 */
VTD_FR_MAX, /* Guard */
} VTDFaultReason;
@@ -564,6 +565,8 @@ typedef struct VTDRootEntry VTDRootEntry;
#define VTD_FL_P 1ULL
#define VTD_FL_RW (1ULL << 1)
#define VTD_FL_US (1ULL << 2)
+#define VTD_FL_A (1ULL << 5)
+#define VTD_FL_D (1ULL << 6)
/* Second Level Page Translation Pointer*/
#define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index d53ce01e82..0aeb0dbde9 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1806,6 +1806,7 @@ static const bool vtd_qualified_faults[] = {
[VTD_FR_FS_PAGING_ENTRY_US] = true,
[VTD_FR_SM_WRITE] = true,
[VTD_FR_SM_INTERRUPT_ADDR] = true,
+ [VTD_FR_FS_BIT_UPDATE_FAILED] = true,
[VTD_FR_MAX] = false,
};
@@ -1925,6 +1926,20 @@ static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova,
}
}
+static MemTxResult vtd_set_flag_in_pte(dma_addr_t base_addr, uint32_t index,
+ uint64_t pte, uint64_t flag)
+{
+ if (pte & flag) {
+ return MEMTX_OK;
+ }
+ pte |= flag;
+ pte = cpu_to_le64(pte);
+ return dma_memory_write(&address_space_memory,
+ base_addr + index * sizeof(pte),
+ &pte, sizeof(pte),
+ MEMTXATTRS_UNSPECIFIED);
+}
+
/*
* Given the @iova, get relevant @flptep. @flpte_level will be the last level
* of the translation, can be used for deciding the size of large page.
@@ -1938,7 +1953,7 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce,
dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce, pasid);
uint32_t level = vtd_get_iova_level(s, ce, pasid);
uint32_t offset;
- uint64_t flpte;
+ uint64_t flpte, flag_ad = VTD_FL_A;
if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) {
error_report_once("%s: detected non canonical IOVA (iova=0x%" PRIx64 ","
@@ -1985,6 +2000,14 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce,
return -VTD_FR_FS_PAGING_ENTRY_RSVD;
}
+ if (vtd_is_last_pte(flpte, level) && is_write) {
+ flag_ad |= VTD_FL_D;
+ }
+
+ if (vtd_set_flag_in_pte(addr, offset, flpte, flag_ad) != MEMTX_OK) {
+ return -VTD_FR_FS_BIT_UPDATE_FAILED;
+ }
+
if (vtd_is_last_pte(flpte, level)) {
*flptep = flpte;
*flpte_level = level;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (13 preceding siblings ...)
2025-01-15 18:09 ` [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 16/48] intel_iommu: Process PASID-based " Michael S. Tsirkin
` (35 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Clément Mathieu--Drif,
Jason Wang, Yi Liu, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
According to spec, Page-Selective-within-Domain Invalidation (11b):
1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through
(PGTT=100b) mappings associated with the specified domain-id and the
input-address range are invalidated.
2. IOTLB entries caching first-stage (PGTT=001b) or nested (PGTT=011b)
mapping associated with specified domain-id are invalidated.
So per spec definition the Page-Selective-within-Domain Invalidation
needs to flush first stage and nested cached IOTLB entries as well.
We don't support nested yet and pass-through mapping is never cached,
so what in iotlb cache are only first-stage and second-stage mappings.
Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and
invalidate entries based on PGTT type.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-11-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 27 +++++++++++++++++++++------
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index f44f3eb63a..a434c2489c 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -155,6 +155,7 @@ struct VTDIOTLBEntry {
uint64_t pte;
uint64_t mask;
uint8_t access_flags;
+ uint8_t pgtt;
};
/* VT-d Source-ID Qualifier types */
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 0aeb0dbde9..95f344eb46 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -305,9 +305,21 @@ static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
- return (entry->domain_id == info->domain_id) &&
- (((entry->gfn & info->mask) == gfn) ||
- (entry->gfn == gfn_tlb));
+
+ if (entry->domain_id != info->domain_id) {
+ return false;
+ }
+
+ /*
+ * According to spec, IOTLB entries caching first-stage (PGTT=001b) or
+ * nested (PGTT=011b) mapping associated with specified domain-id are
+ * invalidated. Nested isn't supported yet, so only need to check 001b.
+ */
+ if (entry->pgtt == VTD_SM_PASID_ENTRY_FLT) {
+ return true;
+ }
+
+ return (entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb;
}
/* Reset all the gen of VTDAddressSpace to zero and set the gen of
@@ -382,7 +394,7 @@ out:
static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
uint16_t domain_id, hwaddr addr, uint64_t pte,
uint8_t access_flags, uint32_t level,
- uint32_t pasid)
+ uint32_t pasid, uint8_t pgtt)
{
VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
struct vtd_iotlb_key *key = g_malloc(sizeof(*key));
@@ -400,6 +412,7 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
entry->access_flags = access_flags;
entry->mask = vtd_pt_level_page_mask(level);
entry->pasid = pasid;
+ entry->pgtt = pgtt;
key->gfn = gfn;
key->sid = source_id;
@@ -2062,7 +2075,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
bool is_fpd_set = false;
bool reads = true;
bool writes = true;
- uint8_t access_flags;
+ uint8_t access_flags, pgtt;
bool rid2pasid = (pasid == PCI_NO_PASID) && s->root_scalable;
VTDIOTLBEntry *iotlb_entry;
uint64_t xlat, size;
@@ -2171,9 +2184,11 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
if (s->flts && s->root_scalable) {
ret_fr = vtd_iova_to_flpte(s, &ce, addr, is_write, &pte, &level,
&reads, &writes, s->aw_bits, pasid);
+ pgtt = VTD_SM_PASID_ENTRY_FLT;
} else {
ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level,
&reads, &writes, s->aw_bits, pasid);
+ pgtt = VTD_SM_PASID_ENTRY_SLT;
}
if (!ret_fr) {
xlat = vtd_get_pte_addr(pte, s->aw_bits);
@@ -2207,7 +2222,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
page_mask = vtd_pt_level_page_mask(level);
access_flags = IOMMU_ACCESS_FLAG(reads, writes);
vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce, pasid),
- addr, pte, access_flags, level, pasid);
+ addr, pte, access_flags, level, pasid, pgtt);
out:
vtd_iommu_unlock(s);
entry->iova = addr & page_mask;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 16/48] intel_iommu: Process PASID-based iotlb invalidation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (14 preceding siblings ...)
2025-01-15 18:09 ` [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID Michael S. Tsirkin
` (34 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Yi Liu, Clément Mathieu--Drif,
Jason Wang, Marcel Apfelbaum, Paolo Bonzini, Richard Henderson,
Eduardo Habkost
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-12-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 3 +++
hw/i386/intel_iommu.c | 43 ++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 22dd3faf0c..5e4e563e62 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -471,6 +471,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4)
#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL)
+#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1)
+#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL)
#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL
#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 95f344eb46..c45a486bf8 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -322,6 +322,28 @@ static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
return (entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb;
}
+static gboolean vtd_hash_remove_by_page_piotlb(gpointer key, gpointer value,
+ gpointer user_data)
+{
+ VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
+ VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
+ uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
+ uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
+
+ /*
+ * According to spec, PASID-based-IOTLB Invalidation in page granularity
+ * doesn't invalidate IOTLB entries caching second-stage (PGTT=010b)
+ * or pass-through (PGTT=100b) mappings. Nested isn't supported yet,
+ * so only need to check first-stage (PGTT=001b) mappings.
+ */
+ if (entry->pgtt != VTD_SM_PASID_ENTRY_FLT) {
+ return false;
+ }
+
+ return entry->domain_id == info->domain_id && entry->pasid == info->pasid &&
+ ((entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb);
+}
+
/* Reset all the gen of VTDAddressSpace to zero and set the gen of
* IntelIOMMUState to 1. Must be called with IOMMU lock held.
*/
@@ -2937,11 +2959,29 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
}
}
+static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
+ uint32_t pasid, hwaddr addr, uint8_t am)
+{
+ VTDIOTLBPageInvInfo info;
+
+ info.domain_id = domain_id;
+ info.pasid = pasid;
+ info.addr = addr;
+ info.mask = ~((1 << am) - 1);
+
+ vtd_iommu_lock(s);
+ g_hash_table_foreach_remove(s->iotlb,
+ vtd_hash_remove_by_page_piotlb, &info);
+ vtd_iommu_unlock(s);
+}
+
static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
uint16_t domain_id;
uint32_t pasid;
+ hwaddr addr;
+ uint8_t am;
uint64_t mask[4] = {VTD_INV_DESC_PIOTLB_RSVD_VAL0,
VTD_INV_DESC_PIOTLB_RSVD_VAL1,
VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE};
@@ -2959,6 +2999,9 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
break;
case VTD_INV_DESC_PIOTLB_PSI_IN_PASID:
+ am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]);
+ addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]);
+ vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am);
break;
default:
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (15 preceding siblings ...)
2025-01-15 18:09 ` [PULL 16/48] intel_iommu: Process PASID-based " Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation Michael S. Tsirkin
` (33 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Clément Mathieu--Drif, Zhenzhong Duan,
Jason Wang, Yi Liu, Paolo Bonzini, Richard Henderson,
Eduardo Habkost, Marcel Apfelbaum
From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
This will be used to implement the device IOTLB invalidation
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-13-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 40 ++++++++++++++++++++++++----------------
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c45a486bf8..9aa807593e 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -70,6 +70,11 @@ struct vtd_hiod_key {
uint8_t devfn;
};
+struct vtd_as_raw_key {
+ uint16_t sid;
+ uint32_t pasid;
+};
+
struct vtd_iotlb_key {
uint64_t gfn;
uint32_t pasid;
@@ -1859,29 +1864,32 @@ static inline bool vtd_is_interrupt_addr(hwaddr addr)
return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
}
-static gboolean vtd_find_as_by_sid(gpointer key, gpointer value,
- gpointer user_data)
+static gboolean vtd_find_as_by_sid_and_pasid(gpointer key, gpointer value,
+ gpointer user_data)
{
struct vtd_as_key *as_key = (struct vtd_as_key *)key;
- uint16_t target_sid = *(uint16_t *)user_data;
+ struct vtd_as_raw_key *target = (struct vtd_as_raw_key *)user_data;
uint16_t sid = PCI_BUILD_BDF(pci_bus_num(as_key->bus), as_key->devfn);
- return sid == target_sid;
+
+ return (as_key->pasid == target->pasid) && (sid == target->sid);
+}
+
+static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(IntelIOMMUState *s,
+ uint16_t sid,
+ uint32_t pasid)
+{
+ struct vtd_as_raw_key key = {
+ .sid = sid,
+ .pasid = pasid
+ };
+
+ return g_hash_table_find(s->vtd_address_spaces,
+ vtd_find_as_by_sid_and_pasid, &key);
}
static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)
{
- uint8_t bus_num = PCI_BUS_NUM(sid);
- VTDAddressSpace *vtd_as = s->vtd_as_cache[bus_num];
-
- if (vtd_as &&
- (sid == PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn))) {
- return vtd_as;
- }
-
- vtd_as = g_hash_table_find(s->vtd_address_spaces, vtd_find_as_by_sid, &sid);
- s->vtd_as_cache[bus_num] = vtd_as;
-
- return vtd_as;
+ return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID);
}
static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (16 preceding siblings ...)
2025-01-15 18:09 ` [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap Michael S. Tsirkin
` (32 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Clément Mathieu--Drif, Zhenzhong Duan,
Jason Wang, Yi Liu, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost
From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-14-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 11 ++++++++
hw/i386/intel_iommu.c | 50 ++++++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 5e4e563e62..2c977aa7da 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -385,6 +385,7 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */
#define VTD_INV_DESC_PIOTLB 0x6 /* PASID-IOTLB Invalidate Desc */
#define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalidate Desc */
+#define VTD_INV_DESC_DEV_PIOTLB 0x8 /* PASID-based-DIOTLB inv_desc*/
#define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */
/* Masks for Invalidation Wait Descriptor*/
@@ -426,6 +427,16 @@ typedef union VTDInvDesc VTDInvDesc;
/* Masks for Interrupt Entry Invalidate Descriptor */
#define VTD_INV_DESC_IEC_RSVD 0xffff000007fff1e0ULL
+/* Masks for PASID based Device IOTLB Invalidate Descriptor */
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(val) ((val) & \
+ 0xfffffffffffff000ULL)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(val) ((val >> 11) & 0x1)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(val) ((val) & 0x1)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(val) (((val) >> 16) & 0xffffULL)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(val) ((val >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL0 0xfff000000000f000ULL
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL1 0x7feULL
+
/* Rsvd field masks for spte */
#define VTD_SPTE_SNP 0x800ULL
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 9aa807593e..5634a37a74 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3075,6 +3075,49 @@ static void do_invalidate_device_tlb(VTDAddressSpace *vtd_dev_as,
memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event);
}
+static bool vtd_process_device_piotlb_desc(IntelIOMMUState *s,
+ VTDInvDesc *inv_desc)
+{
+ uint16_t sid;
+ VTDAddressSpace *vtd_dev_as;
+ bool size;
+ bool global;
+ hwaddr addr;
+ uint32_t pasid;
+ uint64_t mask[4] = {VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL0,
+ VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL1,
+ VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE};
+
+ if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, true,
+ __func__, "device piotlb inv")) {
+ return false;
+ }
+
+ global = VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(inv_desc->hi);
+ size = VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(inv_desc->hi);
+ addr = VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(inv_desc->hi);
+ sid = VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(inv_desc->lo);
+ if (global) {
+ QLIST_FOREACH(vtd_dev_as, &s->vtd_as_with_notifiers, next) {
+ if ((vtd_dev_as->pasid != PCI_NO_PASID) &&
+ (PCI_BUILD_BDF(pci_bus_num(vtd_dev_as->bus),
+ vtd_dev_as->devfn) == sid)) {
+ do_invalidate_device_tlb(vtd_dev_as, size, addr);
+ }
+ }
+ } else {
+ pasid = VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(inv_desc->lo);
+ vtd_dev_as = vtd_get_as_by_sid_and_pasid(s, sid, pasid);
+ if (!vtd_dev_as) {
+ return true;
+ }
+
+ do_invalidate_device_tlb(vtd_dev_as, size, addr);
+ }
+
+ return true;
+}
+
static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -3161,6 +3204,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
}
break;
+ case VTD_INV_DESC_DEV_PIOTLB:
+ trace_vtd_inv_desc("device-piotlb", inv_desc.hi, inv_desc.lo);
+ if (!vtd_process_device_piotlb_desc(s, &inv_desc)) {
+ return false;
+ }
+ break;
+
case VTD_INV_DESC_DEVICE:
trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (17 preceding siblings ...)
2025-01-15 18:09 ` [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes Michael S. Tsirkin
` (31 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Yi Sun, Jason Wang,
Clément Mathieu--Drif, Yi Liu, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
There is already a similar implementation in iotlb invalidation.
So update vtd_iotlb_page_invalidate_notify() to make it work
also for piotlb invalidation.
For device that does not implement ATS capability or disable
it but still caches the translation result, it is better to
implement ATS cap or enable it if there is need to cache the
translation result.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Message-Id: <20241212083757.605022-15-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 43 ++++++++++++++++++++++++++++++++++---------
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 5634a37a74..7d4b99523d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2450,8 +2450,13 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
}
}
+/*
+ * There is no pasid field in iotlb invalidation descriptor, so PCI_NO_PASID
+ * is passed as parameter. Piotlb invalidation supports pasid, pasid in its
+ * descriptor is passed which should not be PCI_NO_PASID.
+ */
static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
- uint16_t domain_id, hwaddr addr,
+ uint16_t domain_id, hwaddr addr,
uint8_t am, uint32_t pasid)
{
VTDAddressSpace *vtd_as;
@@ -2460,19 +2465,37 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
hwaddr size = (1 << am) * VTD_PAGE_SIZE;
QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) {
- if (pasid != PCI_NO_PASID && pasid != vtd_as->pasid) {
- continue;
- }
ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
vtd_as->devfn, &ce);
if (!ret && domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
+ uint32_t rid2pasid = PCI_NO_PASID;
+
+ if (s->root_scalable) {
+ rid2pasid = VTD_CE_GET_RID2PASID(&ce);
+ }
+
+ /*
+ * In legacy mode, vtd_as->pasid == pasid is always true.
+ * In scalable mode, for vtd address space backing a PCI
+ * device without pasid, needs to compare pasid with
+ * rid2pasid of this device.
+ */
+ if (!(vtd_as->pasid == pasid ||
+ (vtd_as->pasid == PCI_NO_PASID && pasid == rid2pasid))) {
+ continue;
+ }
+
if (vtd_as_has_map_notifier(vtd_as)) {
/*
- * As long as we have MAP notifications registered in
- * any of our IOMMU notifiers, we need to sync the
- * shadow page table.
+ * When stage-1 translation is off, as long as we have MAP
+ * notifications registered in any of our IOMMU notifiers,
+ * we need to sync the shadow page table. Otherwise VFIO
+ * device attaches to nested page table instead of shadow
+ * page table, so no need to sync.
*/
- vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size);
+ if (!s->flts || !s->root_scalable) {
+ vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size);
+ }
} else {
/*
* For UNMAP-only notifiers, we don't need to walk the
@@ -2960,7 +2983,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
continue;
}
- if (!s->flts) {
+ if (!s->flts || !vtd_as_has_map_notifier(vtd_as)) {
vtd_address_space_sync(vtd_as);
}
}
@@ -2981,6 +3004,8 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
g_hash_table_foreach_remove(s->iotlb,
vtd_hash_remove_by_page_piotlb, &info);
vtd_iommu_unlock(s);
+
+ vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, pasid);
}
static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (18 preceding siblings ...)
2025-01-15 18:09 ` [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 21/48] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Michael S. Tsirkin
` (30 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Jason Wang, Igor Mammedov,
Ani Sinha
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-16-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..46f80be9ca 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/x86/q35/DMAR.dmar",
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 21/48] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (19 preceding siblings ...)
2025-01-15 18:09 ` [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 22/48] tests/acpi: q35: Update host address width in DMAR Michael S. Tsirkin
` (29 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Jason Wang,
Clément Mathieu--Drif, Yi Liu, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48. So default
aw_bits to 48 when stage-1 translation is turned on.
For legacy and scalable modes, 48 is the default choice for modern
OS when both 48 and 39 are supported. So it makes sense to set
default to 48 for these two modes too starting from QEMU 9.2.
Use pc_compat_9_1 to handle the compatibility for machines before
9.2.
Suggested-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-17-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/intel_iommu.h | 2 +-
hw/i386/pc.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index a434c2489c..72428fefa4 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -45,7 +45,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
#define DMAR_REG_SIZE 0x230
#define VTD_HOST_AW_39BIT 39
#define VTD_HOST_AW_48BIT 48
-#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
+#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_48BIT
#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
#define DMAR_REPORT_F_INTR (1)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 9334b033f6..b46975c8a4 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -86,6 +86,7 @@ GlobalProperty pc_compat_9_1[] = {
{ "ICH9-LPC", "x-smi-swsmi-timer", "off" },
{ "ICH9-LPC", "x-smi-periodic-timer", "off" },
{ TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" },
+ { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" },
};
const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1);
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 22/48] tests/acpi: q35: Update host address width in DMAR
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (20 preceding siblings ...)
2025-01-15 18:09 ` [PULL 21/48] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation Michael S. Tsirkin
` (28 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Clément Mathieu--Drif,
Igor Mammedov, Ani Sinha
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Differences:
@@ -1,39 +1,39 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/x86/q35/DMAR.dmar, Mon Nov 11 15:31:18 2024
+ * Disassembly of /tmp/aml-SPJ4W2, Mon Nov 11 15:31:18 2024
*
* ACPI Data Table [DMAR]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "DMAR" [DMA Remapping table]
[004h 0004 4] Table Length : 00000078
[008h 0008 1] Revision : 01
-[009h 0009 1] Checksum : 15
+[009h 0009 1] Checksum : 0C
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
-[024h 0036 1] Host Address Width : 26
+[024h 0036 1] Host Address Width : 2F
[025h 0037 1] Flags : 01
[026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 00
[030h 0048 2] Subtable Type : 0000 [Hardware Unit Definition]
[032h 0050 2] Length : 0040
[034h 0052 1] Flags : 00
[035h 0053 1] Reserved : 00
[036h 0054 2] PCI Segment Number : 0000
[038h 0056 8] Register Base Address : 00000000FED90000
[040h 0064 1] Device Scope Type : 03 [IOAPIC Device]
[041h 0065 1] Entry Length : 08
[042h 0066 2] Reserved : 0000
[044h 0068 1] Enumeration ID : 00
[045h 0069 1] PCI Bus Number : FF
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Message-Id: <20241212083757.605022-18-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/x86/q35/DMAR.dmar | Bin 120 -> 120 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 46f80be9ca..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/x86/q35/DMAR.dmar",
diff --git a/tests/data/acpi/x86/q35/DMAR.dmar b/tests/data/acpi/x86/q35/DMAR.dmar
index 0dca6e68ad8a8ca5b981bcfbc745385a63e9f216..0c05976715c6f2f6ec46ef6d37790f86a392b5ea 100644
GIT binary patch
delta 21
ccmb=Z;BxVG460yYU|{5#$R)+7KT$Op05(qqk^lez
delta 21
ccmb=Z;BxVG460yYU|<xT$R)+7Hc>Sg05*ICk^lez
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (21 preceding siblings ...)
2025-01-15 18:09 ` [PULL 22/48] tests/acpi: q35: Update host address width in DMAR Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting Michael S. Tsirkin
` (27 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Jason Wang, Yi Liu, Yi Sun,
Clément Mathieu--Drif, Marcel Apfelbaum, Paolo Bonzini,
Richard Henderson, Eduardo Habkost
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
related to scalable mode translation, thus there are multiple combinations.
This vIOMMU implementation wants to simplify it with a new property "x-flts".
When turned on in scalable mode, stage-1 translation is supported. When turned
on in legacy mode, throw out error.
With stage-1 translation support exposed to user, also accurate the pasid entry
check in vtd_pe_type_check().
Suggested-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Message-Id: <20241212083757.605022-19-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu_internal.h | 2 ++
hw/i386/intel_iommu.c | 28 +++++++++++++++++++---------
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 2c977aa7da..e8b211e8b0 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -195,6 +195,7 @@
#define VTD_ECAP_PASID (1ULL << 40)
#define VTD_ECAP_SMTS (1ULL << 43)
#define VTD_ECAP_SLTS (1ULL << 46)
+#define VTD_ECAP_FLTS (1ULL << 47)
/* CAP_REG */
/* (offset >> 4) << 24 */
@@ -211,6 +212,7 @@
#define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35))
#define VTD_CAP_DRAIN_WRITE (1ULL << 54)
#define VTD_CAP_DRAIN_READ (1ULL << 55)
+#define VTD_CAP_FS1GP (1ULL << 56)
#define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WRITE)
#define VTD_CAP_CM (1ULL << 7)
#define VTD_PASID_ID_SHIFT 20
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 7d4b99523d..0111186f7a 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -803,16 +803,18 @@ static inline bool vtd_is_fl_level_supported(IntelIOMMUState *s, uint32_t level)
}
/* Return true if check passed, otherwise false */
-static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu,
- VTDPASIDEntry *pe)
+static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe)
{
switch (VTD_PE_GET_TYPE(pe)) {
- case VTD_SM_PASID_ENTRY_SLT:
- return true;
- case VTD_SM_PASID_ENTRY_PT:
- return x86_iommu->pt_supported;
case VTD_SM_PASID_ENTRY_FLT:
+ return !!(s->ecap & VTD_ECAP_FLTS);
+ case VTD_SM_PASID_ENTRY_SLT:
+ return !!(s->ecap & VTD_ECAP_SLTS);
case VTD_SM_PASID_ENTRY_NESTED:
+ /* Not support NESTED page table type yet */
+ return false;
+ case VTD_SM_PASID_ENTRY_PT:
+ return !!(s->ecap & VTD_ECAP_PT);
default:
/* Unknown type */
return false;
@@ -861,7 +863,6 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
uint8_t pgtt;
uint32_t index;
dma_addr_t entry_size;
- X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
index = VTD_PASID_TABLE_INDEX(pasid);
entry_size = VTD_PASID_ENTRY_SIZE;
@@ -875,7 +876,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
}
/* Do translation type check */
- if (!vtd_pe_type_check(x86_iommu, pe)) {
+ if (!vtd_pe_type_check(s, pe)) {
return -VTD_FR_PASID_TABLE_ENTRY_INV;
}
@@ -3827,6 +3828,7 @@ static const Property vtd_properties[] = {
VTD_HOST_ADDRESS_WIDTH),
DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
+ DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, flts, FALSE),
DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
@@ -4557,7 +4559,10 @@ static void vtd_cap_init(IntelIOMMUState *s)
}
/* TODO: read cap/ecap from host to decide which cap to be exposed. */
- if (s->scalable_mode) {
+ if (s->flts) {
+ s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_FLTS;
+ s->cap |= VTD_CAP_FS1GP;
+ } else if (s->scalable_mode) {
s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
}
@@ -4736,6 +4741,11 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
}
}
+ if (!s->scalable_mode && s->flts) {
+ error_setg(errp, "x-flts is only available in scalable mode");
+ return false;
+ }
+
if (!s->flts && s->aw_bits != VTD_HOST_AW_39BIT &&
s->aw_bits != VTD_HOST_AW_48BIT) {
error_setg(errp, "%s: supported values for aw-bits are: %d, %d",
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (22 preceding siblings ...)
2025-01-15 18:09 ` [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 25/48] tests/qtest: Add intel-iommu test Michael S. Tsirkin
` (26 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Clément Mathieu--Drif, Yi Liu,
Jason Wang, Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
This gives user flexibility to turn off FS1GP for debug purpose.
It is also useful for future nesting feature. When host IOMMU doesn't
support FS1GP but vIOMMU does, nested page table on host side works
after turning FS1GP off in vIOMMU.
This property has no effect when vIOMMU is in legacy mode or x-flts=off
in scalable modme.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-20-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 72428fefa4..9e92bffd5a 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -307,6 +307,7 @@ struct IntelIOMMUState {
bool dma_drain; /* Whether DMA r/w draining enabled */
bool dma_translation; /* Whether DMA translation supported */
bool pasid; /* Whether to support PASID */
+ bool fs1gp; /* First Stage 1-GByte Page Support */
/* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */
bool stale_tm;
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 0111186f7a..f366c223d0 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3834,6 +3834,7 @@ static const Property vtd_properties[] = {
DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, true),
DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false),
+ DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true),
};
/* Read IRTE entry with specific index */
@@ -4561,7 +4562,9 @@ static void vtd_cap_init(IntelIOMMUState *s)
/* TODO: read cap/ecap from host to decide which cap to be exposed. */
if (s->flts) {
s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_FLTS;
- s->cap |= VTD_CAP_FS1GP;
+ if (s->fs1gp) {
+ s->cap |= VTD_CAP_FS1GP;
+ }
} else if (s->scalable_mode) {
s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
}
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 25/48] tests/qtest: Add intel-iommu test
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (23 preceding siblings ...)
2025-01-15 18:09 ` [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation Michael S. Tsirkin
` (25 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Zhenzhong Duan, Thomas Huth,
Clément Mathieu--Drif, Jason Wang, Yi Liu, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Add the framework to test the intel-iommu device.
Currently only tested cap/ecap bits correctness when x-flts=on in scalable
mode. Also tested cap/ecap bits consistency before and after system reset.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-21-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/intel_iommu.h | 1 +
tests/qtest/intel-iommu-test.c | 64 ++++++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
tests/qtest/meson.build | 1 +
4 files changed, 67 insertions(+)
create mode 100644 tests/qtest/intel-iommu-test.c
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 9e92bffd5a..e95477e855 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -47,6 +47,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
#define VTD_HOST_AW_48BIT 48
#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_48BIT
#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
+#define VTD_MGAW_FROM_CAP(cap) ((cap >> 16) & 0x3fULL)
#define DMAR_REPORT_F_INTR (1)
diff --git a/tests/qtest/intel-iommu-test.c b/tests/qtest/intel-iommu-test.c
new file mode 100644
index 0000000000..c521b3796e
--- /dev/null
+++ b/tests/qtest/intel-iommu-test.c
@@ -0,0 +1,64 @@
+/*
+ * QTest testcase for intel-iommu
+ *
+ * Copyright (c) 2024 Intel, Inc.
+ *
+ * Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "hw/i386/intel_iommu_internal.h"
+
+#define CAP_STAGE_1_FIXED1 (VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | \
+ VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS)
+#define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \
+ VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FLTS)
+
+static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset)
+{
+ return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);
+}
+
+static void test_intel_iommu_stage_1(void)
+{
+ uint8_t init_csr[DMAR_REG_SIZE]; /* register values */
+ uint8_t post_reset_csr[DMAR_REG_SIZE]; /* register values */
+ uint64_t cap, ecap, tmp;
+ QTestState *s;
+
+ s = qtest_init("-M q35 -device intel-iommu,x-scalable-mode=on,x-flts=on");
+
+ cap = vtd_reg_readq(s, DMAR_CAP_REG);
+ g_assert((cap & CAP_STAGE_1_FIXED1) == CAP_STAGE_1_FIXED1);
+
+ tmp = cap & VTD_CAP_SAGAW_MASK;
+ g_assert(tmp == (VTD_CAP_SAGAW_39bit | VTD_CAP_SAGAW_48bit));
+
+ tmp = VTD_MGAW_FROM_CAP(cap);
+ g_assert(tmp == VTD_HOST_AW_48BIT - 1);
+
+ ecap = vtd_reg_readq(s, DMAR_ECAP_REG);
+ g_assert((ecap & ECAP_STAGE_1_FIXED1) == ECAP_STAGE_1_FIXED1);
+
+ qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, init_csr, DMAR_REG_SIZE);
+
+ qobject_unref(qtest_qmp(s, "{ 'execute': 'system_reset' }"));
+ qtest_qmp_eventwait(s, "RESET");
+
+ qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, post_reset_csr, DMAR_REG_SIZE);
+ /* Ensure registers are consistent after hard reset */
+ g_assert(!memcmp(init_csr, post_reset_csr, DMAR_REG_SIZE));
+
+ qtest_quit(s);
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+ qtest_add_func("/q35/intel-iommu/stage-1", test_intel_iommu_stage_1);
+
+ return g_test_run();
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index 8b9d9a7cac..a928ce3e41 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3711,6 +3711,7 @@ F: hw/i386/intel_iommu.c
F: hw/i386/intel_iommu_internal.h
F: include/hw/i386/intel_iommu.h
F: tests/functional/test_intel_iommu.py
+F: tests/qtest/intel-iommu-test.c
AMD-Vi Emulation
S: Orphan
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index bf4d5c268b..edd53ec995 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -93,6 +93,7 @@ qtests_i386 = \
(config_all_devices.has_key('CONFIG_SB16') ? ['fuzz-sb16-test'] : []) + \
(config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : []) + \
(config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) + \
(host_os != 'windows' and \
config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + \
(config_all_devices.has_key('CONFIG_PCIE_PORT') and \
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (24 preceding siblings ...)
2025-01-15 18:09 ` [PULL 25/48] tests/qtest: Add intel-iommu test Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED Michael S. Tsirkin
` (24 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Nicholas Piggin, Philippe Mathieu-Daudé,
Marcel Apfelbaum
From: Nicholas Piggin <npiggin@gmail.com>
The end vector calculation has a bug that results in polling fewer
than required vectors when reading at a non-zero offset in PBA memory.
Fixes: bbef882cc193 ("msi: add API to get notified about pending bit poll")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20241212120402.1475053-1-npiggin@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/pci/msix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index d8a55a6474..57ec7084a4 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -250,7 +250,7 @@ static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
PCIDevice *dev = opaque;
if (dev->msix_vector_poll_notifier) {
unsigned vector_start = addr * 8;
- unsigned vector_end = MIN(addr + size * 8, dev->msix_entries_nr);
+ unsigned vector_end = MIN((addr + size) * 8, dev->msix_entries_nr);
dev->msix_vector_poll_notifier(dev, vector_start, vector_end);
}
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (25 preceding siblings ...)
2025-01-15 18:09 ` [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 28/48] acpi/ghes: simplify acpi_ghes_record_errors() code Michael S. Tsirkin
` (23 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Igor Mammedov,
Jonathan Cameron, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which
has a better name. So, drop the duplication.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <9012bf4c9630adf15a22af3c88fda8270916887b.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/ghes.h | 3 ++-
hw/acpi/ghes.c | 7 ++-----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h
index 674f6958e9..59e3b8fb24 100644
--- a/include/hw/acpi/ghes.h
+++ b/include/hw/acpi/ghes.h
@@ -59,7 +59,8 @@ enum AcpiGhesNotifyType {
enum {
ACPI_HEST_SRC_ID_SEA = 0,
/* future ids go here */
- ACPI_HEST_SRC_ID_RESERVED,
+
+ ACPI_GHES_ERROR_SOURCE_COUNT
};
typedef struct AcpiGhesState {
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index e9511d9b8f..dc217694de 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -34,9 +34,6 @@
/* The max size in bytes for one error block */
#define ACPI_GHES_MAX_RAW_DATA_LENGTH (1 * KiB)
-/* Now only support ARMv8 SEA notification type error source */
-#define ACPI_GHES_ERROR_SOURCE_COUNT 1
-
/* Generic Hardware Error Source version 2 */
#define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10
@@ -396,7 +393,7 @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address)
AcpiGedState *acpi_ged_state;
AcpiGhesState *ags;
- assert(source_id < ACPI_HEST_SRC_ID_RESERVED);
+ assert(source_id < ACPI_GHES_ERROR_SOURCE_COUNT);
acpi_ged_state = ACPI_GED(object_resolve_path_type("", TYPE_ACPI_GED,
NULL));
@@ -407,7 +404,7 @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address)
if (physical_address) {
- if (source_id < ACPI_HEST_SRC_ID_RESERVED) {
+ if (source_id < ACPI_GHES_ERROR_SOURCE_COUNT) {
start_addr += source_id * sizeof(uint64_t);
}
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 28/48] acpi/ghes: simplify acpi_ghes_record_errors() code
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (26 preceding siblings ...)
2025-01-15 18:09 ` [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table Michael S. Tsirkin
` (22 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Igor Mammedov,
Jonathan Cameron, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reduce the ident of the function and prepares it for
the next changes.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <19af4188535217213486d169e0501e592bc78a95.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ghes.c | 56 ++++++++++++++++++++++++++------------------------
1 file changed, 29 insertions(+), 27 deletions(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index dc217694de..e66f3be150 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -402,40 +402,42 @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address)
start_addr = le64_to_cpu(ags->ghes_addr_le);
- if (physical_address) {
+ if (!physical_address) {
+ return -1;
+ }
- if (source_id < ACPI_GHES_ERROR_SOURCE_COUNT) {
- start_addr += source_id * sizeof(uint64_t);
- }
+ if (source_id < ACPI_GHES_ERROR_SOURCE_COUNT) {
+ start_addr += source_id * sizeof(uint64_t);
+ }
- cpu_physical_memory_read(start_addr, &error_block_addr,
- sizeof(error_block_addr));
+ cpu_physical_memory_read(start_addr, &error_block_addr,
+ sizeof(error_block_addr));
- error_block_addr = le64_to_cpu(error_block_addr);
+ error_block_addr = le64_to_cpu(error_block_addr);
- read_ack_register_addr = start_addr +
- ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t);
+ read_ack_register_addr = start_addr +
+ ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t);
- cpu_physical_memory_read(read_ack_register_addr,
- &read_ack_register, sizeof(read_ack_register));
+ cpu_physical_memory_read(read_ack_register_addr,
+ &read_ack_register, sizeof(read_ack_register));
- /* zero means OSPM does not acknowledge the error */
- if (!read_ack_register) {
- error_report("OSPM does not acknowledge previous error,"
- " so can not record CPER for current error anymore");
- } else if (error_block_addr) {
- read_ack_register = cpu_to_le64(0);
- /*
- * Clear the Read Ack Register, OSPM will write it to 1 when
- * it acknowledges this error.
- */
- cpu_physical_memory_write(read_ack_register_addr,
- &read_ack_register, sizeof(uint64_t));
+ /* zero means OSPM does not acknowledge the error */
+ if (!read_ack_register) {
+ error_report("OSPM does not acknowledge previous error,"
+ " so can not record CPER for current error anymore");
+ } else if (error_block_addr) {
+ read_ack_register = cpu_to_le64(0);
+ /*
+ * Clear the Read Ack Register, OSPM will write it to 1 when
+ * it acknowledges this error.
+ */
+ cpu_physical_memory_write(read_ack_register_addr,
+ &read_ack_register, sizeof(uint64_t));
- ret = acpi_ghes_record_mem_error(error_block_addr,
- physical_address);
- } else
- error_report("can not find Generic Error Status Block");
+ ret = acpi_ghes_record_mem_error(error_block_addr,
+ physical_address);
+ } else {
+ error_report("can not find Generic Error Status Block");
}
return ret;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (27 preceding siblings ...)
2025-01-15 18:09 ` [PULL 28/48] acpi/ghes: simplify acpi_ghes_record_errors() code Michael S. Tsirkin
@ 2025-01-15 18:09 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 30/48] acpi/ghes: better handle source_id and notification Michael S. Tsirkin
` (21 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:09 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Ani Sinha, Dongjiu Geng, Shannon Zhao, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
The GHES driver requires not only a HEST table, but also a
separate firmware file to store Error Structure records.
It can't do one without the other.
Simplify the caller logic for it to require one function.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <9584bb8953385e165681d5d185c503f8df8ef42f.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/ghes.h | 4 ++--
hw/acpi/ghes.c | 7 +++++--
hw/arm/virt-acpi-build.c | 5 ++---
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h
index 59e3b8fb24..20016c226d 100644
--- a/include/hw/acpi/ghes.h
+++ b/include/hw/acpi/ghes.h
@@ -68,8 +68,8 @@ typedef struct AcpiGhesState {
bool present; /* True if GHES is present at all on this board */
} AcpiGhesState;
-void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker);
-void acpi_build_hest(GArray *table_data, BIOSLinker *linker,
+void acpi_build_hest(GArray *table_data, GArray *hardware_errors,
+ BIOSLinker *linker,
const char *oem_id, const char *oem_table_id);
void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s,
GArray *hardware_errors);
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index e66f3be150..4a6c45bcb4 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -233,7 +233,7 @@ static int acpi_ghes_record_mem_error(uint64_t error_block_address,
* Initialize "etc/hardware_errors" and "etc/hardware_errors_addr" fw_cfg blobs.
* See docs/specs/acpi_hest_ghes.rst for blobs format.
*/
-void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker)
+static void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker)
{
int i, error_status_block_offset;
@@ -356,12 +356,15 @@ static void build_ghes_v2(GArray *table_data, int source_id, BIOSLinker *linker)
}
/* Build Hardware Error Source Table */
-void acpi_build_hest(GArray *table_data, BIOSLinker *linker,
+void acpi_build_hest(GArray *table_data, GArray *hardware_errors,
+ BIOSLinker *linker,
const char *oem_id, const char *oem_table_id)
{
AcpiTable table = { .sig = "HEST", .rev = 1,
.oem_id = oem_id, .oem_table_id = oem_table_id };
+ build_ghes_error_table(hardware_errors, linker);
+
acpi_table_begin(&table, table_data);
/* Error Source Count */
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index c9b13057a3..3ac8f8e178 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -946,10 +946,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
build_dbg2(tables_blob, tables->linker, vms);
if (vms->ras) {
- build_ghes_error_table(tables->hardware_errors, tables->linker);
acpi_add_table(table_offsets, tables_blob);
- acpi_build_hest(tables_blob, tables->linker, vms->oem_id,
- vms->oem_table_id);
+ acpi_build_hest(tables_blob, tables->hardware_errors, tables->linker,
+ vms->oem_id, vms->oem_table_id);
}
if (ms->numa_state->num_nodes > 0) {
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 30/48] acpi/ghes: better handle source_id and notification
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (28 preceding siblings ...)
2025-01-15 18:09 ` [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument Michael S. Tsirkin
` (20 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
GHES has two fields that are stored on HEST error source
blocks associated with notifications:
- notification type, which is a number defined at the ACPI spec
containing several arch-specific synchronous and assynchronous
types;
- source id, which is a HW/FW defined number, used to distinguish
between different implemented sources.
There could be several sources with the same notification type,
which is dependent of the way each architecture maps notifications.
Right now, build_ghes_v2() hardcodes a 1:1 mapping between such
fields. Move it to two independent parameters, allowing the
caller function to fill both.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <133ff72ea1041fed7dbcf97b7a2b0f4dfacde31a.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ghes.c | 23 +++++++++--------------
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 4a6c45bcb4..29cd7e4d81 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -284,9 +284,13 @@ static void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker)
}
/* Build Generic Hardware Error Source version 2 (GHESv2) */
-static void build_ghes_v2(GArray *table_data, int source_id, BIOSLinker *linker)
+static void build_ghes_v2(GArray *table_data,
+ BIOSLinker *linker,
+ enum AcpiGhesNotifyType notify,
+ uint16_t source_id)
{
uint64_t address_offset;
+
/*
* Type:
* Generic Hardware Error Source version 2(GHESv2 - Type 10)
@@ -316,18 +320,8 @@ static void build_ghes_v2(GArray *table_data, int source_id, BIOSLinker *linker)
address_offset + GAS_ADDR_OFFSET, sizeof(uint64_t),
ACPI_GHES_ERRORS_FW_CFG_FILE, source_id * sizeof(uint64_t));
- switch (source_id) {
- case ACPI_HEST_SRC_ID_SEA:
- /*
- * Notification Structure
- * Now only enable ARMv8 SEA notification type
- */
- build_ghes_hw_error_notification(table_data, ACPI_GHES_NOTIFY_SEA);
- break;
- default:
- error_report("Not support this error source");
- abort();
- }
+ /* Notification Structure */
+ build_ghes_hw_error_notification(table_data, notify);
/* Error Status Block Length */
build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4);
@@ -369,7 +363,8 @@ void acpi_build_hest(GArray *table_data, GArray *hardware_errors,
/* Error Source Count */
build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4);
- build_ghes_v2(table_data, ACPI_HEST_SRC_ID_SEA, linker);
+ build_ghes_v2(table_data, linker,
+ ACPI_GHES_NOTIFY_SEA, ACPI_HEST_SRC_ID_SEA);
acpi_table_end(linker, &table);
}
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (29 preceding siblings ...)
2025-01-15 18:10 ` [PULL 30/48] acpi/ghes: better handle source_id and notification Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check Michael S. Tsirkin
` (19 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Align the header file with the actual implementation of
this function, as the first argument is source ID and not
notification type.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <d55f2a6ede5a168e42a20a228b2c066cb4c60939.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/ghes.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h
index 20016c226d..50e3a25ea3 100644
--- a/include/hw/acpi/ghes.h
+++ b/include/hw/acpi/ghes.h
@@ -73,7 +73,7 @@ void acpi_build_hest(GArray *table_data, GArray *hardware_errors,
const char *oem_id, const char *oem_table_id);
void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s,
GArray *hardware_errors);
-int acpi_ghes_record_errors(uint8_t notify, uint64_t error_physical_addr);
+int acpi_ghes_record_errors(uint8_t source_id, uint64_t error_physical_addr);
/**
* acpi_ghes_present: Report whether ACPI GHES table is present
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (30 preceding siblings ...)
2025-01-15 18:10 ` [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 33/48] acpi/ghes: Change the type for source_id Michael S. Tsirkin
` (18 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Igor Mammedov,
Jonathan Cameron, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
acpi_ghes_record_errors() has an assert() at the beginning
to ensure that source_id will be lower than
ACPI_GHES_ERROR_SOURCE_COUNT. Remove a duplicated check.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <df33b004d85b7b9aa388fb2ac530dcdea94b7edc.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ghes.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 29cd7e4d81..5f67322bf0 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -404,9 +404,7 @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address)
return -1;
}
- if (source_id < ACPI_GHES_ERROR_SOURCE_COUNT) {
- start_addr += source_id * sizeof(uint64_t);
- }
+ start_addr += source_id * sizeof(uint64_t);
cpu_physical_memory_read(start_addr, &error_block_addr,
sizeof(error_block_addr));
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 33/48] acpi/ghes: Change the type for source_id
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (31 preceding siblings ...)
2025-01-15 18:10 ` [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 34/48] acpi/ghes: don't check if physical_address is not zero Michael S. Tsirkin
` (17 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
As described at: ACPI 6.5 spec at:
18.3.2. ACPI Error Source
In particular at GHES/GHESv2 table:
Table 18.10 Generic Hardware Error Source Structure
HEST source ID is actually a 16-bit value.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <0e83ba548c1aedd1299fe387b94db78986590a34.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/ghes.h | 2 +-
hw/acpi/ghes-stub.c | 2 +-
hw/acpi/ghes.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h
index 50e3a25ea3..9295e46be2 100644
--- a/include/hw/acpi/ghes.h
+++ b/include/hw/acpi/ghes.h
@@ -73,7 +73,7 @@ void acpi_build_hest(GArray *table_data, GArray *hardware_errors,
const char *oem_id, const char *oem_table_id);
void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s,
GArray *hardware_errors);
-int acpi_ghes_record_errors(uint8_t source_id, uint64_t error_physical_addr);
+int acpi_ghes_record_errors(uint16_t source_id, uint64_t error_physical_addr);
/**
* acpi_ghes_present: Report whether ACPI GHES table is present
diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c
index c315de1802..2b64cbd281 100644
--- a/hw/acpi/ghes-stub.c
+++ b/hw/acpi/ghes-stub.c
@@ -11,7 +11,7 @@
#include "qemu/osdep.h"
#include "hw/acpi/ghes.h"
-int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address)
+int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
{
return -1;
}
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 5f67322bf0..edc74c38bf 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -383,7 +383,7 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s,
ags->present = true;
}
-int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address)
+int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
{
uint64_t error_block_addr, read_ack_register_addr, read_ack_register = 0;
uint64_t start_addr;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 34/48] acpi/ghes: don't check if physical_address is not zero
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (32 preceding siblings ...)
2025-01-15 18:10 ` [PULL 33/48] acpi/ghes: Change the type for source_id Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 35/48] acpi/ghes: make the GHES record generation more generic Michael S. Tsirkin
` (16 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Igor Mammedov,
Jonathan Cameron, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
The 'physical_address' value is a faulty page. As such, 0 is
as valid as any other value.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <da32536bf4962e5c03471e2a4e6e0ef92be4a1be.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ghes.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index edc74c38bf..a3dffd78b0 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -400,10 +400,6 @@ int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
start_addr = le64_to_cpu(ags->ghes_addr_le);
- if (!physical_address) {
- return -1;
- }
-
start_addr += source_id * sizeof(uint64_t);
cpu_physical_memory_read(start_addr, &error_block_addr,
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 35/48] acpi/ghes: make the GHES record generation more generic
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (33 preceding siblings ...)
2025-01-15 18:10 ` [PULL 34/48] acpi/ghes: don't check if physical_address is not zero Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 36/48] acpi/ghes: better name GHES memory error function Michael S. Tsirkin
` (15 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Igor Mammedov,
Jonathan Cameron, Dongjiu Geng, Ani Sinha, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Split the code into separate functions to allow using the
common CPER filling code by different error sources.
The generic code was moved to ghes_record_cper_errors(),
and ghes_gen_err_data_uncorrectable_recoverable() now contains
only a logic to fill the Generic Error Data part of the record,
as described at:
ACPI 6.2: 18.3.2.7.1 Generic Error Data
The remaining code to generate a memory error now belongs to
acpi_ghes_record_errors() function.
A further patch will give it a better name.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <68d9f787d8c4fc8d1dbc227d6902fe801e42dea9.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/ghes.h | 3 ++
hw/acpi/ghes.c | 120 +++++++++++++++++++++++------------------
2 files changed, 72 insertions(+), 51 deletions(-)
diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h
index 9295e46be2..8859346af5 100644
--- a/include/hw/acpi/ghes.h
+++ b/include/hw/acpi/ghes.h
@@ -23,6 +23,7 @@
#define ACPI_GHES_H
#include "hw/acpi/bios-linker-loader.h"
+#include "qapi/error.h"
/*
* Values for Hardware Error Notification Type field
@@ -73,6 +74,8 @@ void acpi_build_hest(GArray *table_data, GArray *hardware_errors,
const char *oem_id, const char *oem_table_id);
void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s,
GArray *hardware_errors);
+void ghes_record_cper_errors(const void *cper, size_t len,
+ uint16_t source_id, Error **errp);
int acpi_ghes_record_errors(uint16_t source_id, uint64_t error_physical_addr);
/**
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index a3dffd78b0..6f40cd35a9 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -181,51 +181,24 @@ static void acpi_ghes_build_append_mem_cper(GArray *table,
build_append_int_noprefix(table, 0, 7);
}
-static int acpi_ghes_record_mem_error(uint64_t error_block_address,
- uint64_t error_physical_addr)
+static void
+ghes_gen_err_data_uncorrectable_recoverable(GArray *block,
+ const uint8_t *section_type,
+ int data_length)
{
- GArray *block;
-
- /* Memory Error Section Type */
- const uint8_t uefi_cper_mem_sec[] =
- UUID_LE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
- 0xED, 0x7C, 0x83, 0xB1);
-
/* invalid fru id: ACPI 4.0: 17.3.2.6.1 Generic Error Data,
* Table 17-13 Generic Error Data Entry
*/
QemuUUID fru_id = {};
- uint32_t data_length;
-
- block = g_array_new(false, true /* clear */, 1);
-
- /* This is the length if adding a new generic error data entry*/
- data_length = ACPI_GHES_DATA_LENGTH + ACPI_GHES_MEM_CPER_LENGTH;
- /*
- * It should not run out of the preallocated memory if adding a new generic
- * error data entry
- */
- assert((data_length + ACPI_GHES_GESB_SIZE) <=
- ACPI_GHES_MAX_RAW_DATA_LENGTH);
/* Build the new generic error status block header */
acpi_ghes_generic_error_status(block, ACPI_GEBS_UNCORRECTABLE,
0, 0, data_length, ACPI_CPER_SEV_RECOVERABLE);
/* Build this new generic error data entry header */
- acpi_ghes_generic_error_data(block, uefi_cper_mem_sec,
+ acpi_ghes_generic_error_data(block, section_type,
ACPI_CPER_SEV_RECOVERABLE, 0, 0,
ACPI_GHES_MEM_CPER_LENGTH, fru_id, 0);
-
- /* Build the memory section CPER for above new generic error data entry */
- acpi_ghes_build_append_mem_cper(block, error_physical_addr);
-
- /* Write the generic error data entry into guest memory */
- cpu_physical_memory_write(error_block_address, block->data, block->len);
-
- g_array_free(block, true);
-
- return 0;
}
/*
@@ -383,15 +356,18 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s,
ags->present = true;
}
-int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
+void ghes_record_cper_errors(const void *cper, size_t len,
+ uint16_t source_id, Error **errp)
{
uint64_t error_block_addr, read_ack_register_addr, read_ack_register = 0;
uint64_t start_addr;
- bool ret = -1;
AcpiGedState *acpi_ged_state;
AcpiGhesState *ags;
- assert(source_id < ACPI_GHES_ERROR_SOURCE_COUNT);
+ if (len > ACPI_GHES_MAX_RAW_DATA_LENGTH) {
+ error_setg(errp, "GHES CPER record is too big: %zd", len);
+ return;
+ }
acpi_ged_state = ACPI_GED(object_resolve_path_type("", TYPE_ACPI_GED,
NULL));
@@ -406,6 +382,10 @@ int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
sizeof(error_block_addr));
error_block_addr = le64_to_cpu(error_block_addr);
+ if (!error_block_addr) {
+ error_setg(errp, "can not find Generic Error Status Block");
+ return;
+ }
read_ack_register_addr = start_addr +
ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t);
@@ -415,24 +395,62 @@ int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
/* zero means OSPM does not acknowledge the error */
if (!read_ack_register) {
- error_report("OSPM does not acknowledge previous error,"
- " so can not record CPER for current error anymore");
- } else if (error_block_addr) {
- read_ack_register = cpu_to_le64(0);
- /*
- * Clear the Read Ack Register, OSPM will write it to 1 when
- * it acknowledges this error.
- */
- cpu_physical_memory_write(read_ack_register_addr,
- &read_ack_register, sizeof(uint64_t));
-
- ret = acpi_ghes_record_mem_error(error_block_addr,
- physical_address);
- } else {
- error_report("can not find Generic Error Status Block");
+ error_setg(errp,
+ "OSPM does not acknowledge previous error,"
+ " so can not record CPER for current error anymore");
+ return;
}
- return ret;
+ read_ack_register = cpu_to_le64(0);
+ /*
+ * Clear the Read Ack Register, OSPM will write 1 to this register when
+ * it acknowledges the error.
+ */
+ cpu_physical_memory_write(read_ack_register_addr,
+ &read_ack_register, sizeof(uint64_t));
+
+ /* Write the generic error data entry into guest memory */
+ cpu_physical_memory_write(error_block_addr, cper, len);
+
+ return;
+}
+
+int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
+{
+ /* Memory Error Section Type */
+ const uint8_t guid[] =
+ UUID_LE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \
+ 0xED, 0x7C, 0x83, 0xB1);
+ Error *errp = NULL;
+ int data_length;
+ GArray *block;
+
+ block = g_array_new(false, true /* clear */, 1);
+
+ data_length = ACPI_GHES_DATA_LENGTH + ACPI_GHES_MEM_CPER_LENGTH;
+ /*
+ * It should not run out of the preallocated memory if adding a new generic
+ * error data entry
+ */
+ assert((data_length + ACPI_GHES_GESB_SIZE) <=
+ ACPI_GHES_MAX_RAW_DATA_LENGTH);
+
+ ghes_gen_err_data_uncorrectable_recoverable(block, guid, data_length);
+
+ /* Build the memory section CPER for above new generic error data entry */
+ acpi_ghes_build_append_mem_cper(block, physical_address);
+
+ /* Report the error */
+ ghes_record_cper_errors(block->data, block->len, source_id, &errp);
+
+ g_array_free(block, true);
+
+ if (errp) {
+ error_report_err(errp);
+ return -1;
+ }
+
+ return 0;
}
bool acpi_ghes_present(void)
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 36/48] acpi/ghes: better name GHES memory error function
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (34 preceding siblings ...)
2025-01-15 18:10 ` [PULL 35/48] acpi/ghes: make the GHES record generation more generic Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 37/48] acpi/ghes: don't crash QEMU if ghes GED is not found Michael S. Tsirkin
` (14 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Igor Mammedov,
Jonathan Cameron, Ani Sinha, Dongjiu Geng, Paolo Bonzini,
qemu-arm, kvm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
The current function used to generate GHES data is specific for
memory errors. Give a better name for it, as we now have a generic
function as well.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Message-Id: <35b59121129d5e99cb5062cc3d775594bbb0905b.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/ghes.h | 4 ++--
hw/acpi/ghes-stub.c | 2 +-
hw/acpi/ghes.c | 2 +-
target/arm/kvm.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h
index 8859346af5..21666a4bcc 100644
--- a/include/hw/acpi/ghes.h
+++ b/include/hw/acpi/ghes.h
@@ -74,15 +74,15 @@ void acpi_build_hest(GArray *table_data, GArray *hardware_errors,
const char *oem_id, const char *oem_table_id);
void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s,
GArray *hardware_errors);
+int acpi_ghes_memory_errors(uint16_t source_id, uint64_t error_physical_addr);
void ghes_record_cper_errors(const void *cper, size_t len,
uint16_t source_id, Error **errp);
-int acpi_ghes_record_errors(uint16_t source_id, uint64_t error_physical_addr);
/**
* acpi_ghes_present: Report whether ACPI GHES table is present
*
* Returns: true if the system has an ACPI GHES table and it is
- * safe to call acpi_ghes_record_errors() to record a memory error.
+ * safe to call acpi_ghes_memory_errors() to record a memory error.
*/
bool acpi_ghes_present(void);
#endif
diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c
index 2b64cbd281..7cec1812da 100644
--- a/hw/acpi/ghes-stub.c
+++ b/hw/acpi/ghes-stub.c
@@ -11,7 +11,7 @@
#include "qemu/osdep.h"
#include "hw/acpi/ghes.h"
-int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
+int acpi_ghes_memory_errors(uint16_t source_id, uint64_t physical_address)
{
return -1;
}
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 6f40cd35a9..66bd98337a 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -415,7 +415,7 @@ void ghes_record_cper_errors(const void *cper, size_t len,
return;
}
-int acpi_ghes_record_errors(uint16_t source_id, uint64_t physical_address)
+int acpi_ghes_memory_errors(uint16_t source_id, uint64_t physical_address)
{
/* Memory Error Section Type */
const uint8_t guid[] =
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index a9444a2c7a..da30bdbb23 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -2387,7 +2387,7 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
*/
if (code == BUS_MCEERR_AR) {
kvm_cpu_synchronize_state(c);
- if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr)) {
+ if (!acpi_ghes_memory_errors(ACPI_HEST_SRC_ID_SEA, paddr)) {
kvm_inject_arm_sea(c);
} else {
error_report("failed to record the error");
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 37/48] acpi/ghes: don't crash QEMU if ghes GED is not found
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (35 preceding siblings ...)
2025-01-15 18:10 ` [PULL 36/48] acpi/ghes: better name GHES memory error function Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 38/48] acpi/ghes: rename etc/hardware_error file macros Michael S. Tsirkin
` (13 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Make error handling within ghes_record_cper_errors() consistent,
i.e. instead abort just print a error in case ghes GED is not found.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <c7e1665ba46df321f0ce161d60dfd681ab827535.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ghes.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 66bd98337a..6843ddf64b 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -371,7 +371,10 @@ void ghes_record_cper_errors(const void *cper, size_t len,
acpi_ged_state = ACPI_GED(object_resolve_path_type("", TYPE_ACPI_GED,
NULL));
- g_assert(acpi_ged_state);
+ if (!acpi_ged_state) {
+ error_setg(errp, "Can't find ACPI_GED object");
+ return;
+ }
ags = &acpi_ged_state->ghes_state;
start_addr = le64_to_cpu(ags->ghes_addr_le);
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 38/48] acpi/ghes: rename etc/hardware_error file macros
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (36 preceding siblings ...)
2025-01-15 18:10 ` [PULL 37/48] acpi/ghes: don't crash QEMU if ghes GED is not found Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 39/48] acpi/ghes: better name the offset of the hardware error firmware Michael S. Tsirkin
` (12 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Igor Mammedov,
Jonathan Cameron, Dongjiu Geng, Ani Sinha, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Now that we have also have a file to store HEST data location,
which is part of GHES, better name the file where CPER records
are stored.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <e79a013bcd9f634b46ff6b34756d1b1403713af3.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ghes.c | 38 +++++++++++++++++++++++---------------
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 6843ddf64b..3f94a5542b 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -28,8 +28,8 @@
#include "hw/nvram/fw_cfg.h"
#include "qemu/uuid.h"
-#define ACPI_GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors"
-#define ACPI_GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr"
+#define ACPI_HW_ERROR_FW_CFG_FILE "etc/hardware_errors"
+#define ACPI_HW_ERROR_ADDR_FW_CFG_FILE "etc/hardware_errors_addr"
/* The max size in bytes for one error block */
#define ACPI_GHES_MAX_RAW_DATA_LENGTH (1 * KiB)
@@ -234,7 +234,7 @@ static void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker)
ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT);
/* Tell guest firmware to place hardware_errors blob into RAM */
- bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE,
+ bios_linker_loader_alloc(linker, ACPI_HW_ERROR_FW_CFG_FILE,
hardware_errors, sizeof(uint64_t), false);
for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
@@ -243,17 +243,21 @@ static void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker)
* corresponding "Generic Error Status Block"
*/
bios_linker_loader_add_pointer(linker,
- ACPI_GHES_ERRORS_FW_CFG_FILE, sizeof(uint64_t) * i,
- sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE,
- error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH);
+ ACPI_HW_ERROR_FW_CFG_FILE,
+ sizeof(uint64_t) * i,
+ sizeof(uint64_t),
+ ACPI_HW_ERROR_FW_CFG_FILE,
+ error_status_block_offset +
+ i * ACPI_GHES_MAX_RAW_DATA_LENGTH);
}
/*
* tell firmware to write hardware_errors GPA into
* hardware_errors_addr fw_cfg, once the former has been initialized.
*/
- bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FILE,
- 0, sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE, 0);
+ bios_linker_loader_write_pointer(linker, ACPI_HW_ERROR_ADDR_FW_CFG_FILE, 0,
+ sizeof(uint64_t),
+ ACPI_HW_ERROR_FW_CFG_FILE, 0);
}
/* Build Generic Hardware Error Source version 2 (GHESv2) */
@@ -290,8 +294,10 @@ static void build_ghes_v2(GArray *table_data,
build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0,
4 /* QWord access */, 0);
bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
- address_offset + GAS_ADDR_OFFSET, sizeof(uint64_t),
- ACPI_GHES_ERRORS_FW_CFG_FILE, source_id * sizeof(uint64_t));
+ address_offset + GAS_ADDR_OFFSET,
+ sizeof(uint64_t),
+ ACPI_HW_ERROR_FW_CFG_FILE,
+ source_id * sizeof(uint64_t));
/* Notification Structure */
build_ghes_hw_error_notification(table_data, notify);
@@ -308,9 +314,11 @@ static void build_ghes_v2(GArray *table_data,
build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0,
4 /* QWord access */, 0);
bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
- address_offset + GAS_ADDR_OFFSET,
- sizeof(uint64_t), ACPI_GHES_ERRORS_FW_CFG_FILE,
- (ACPI_GHES_ERROR_SOURCE_COUNT + source_id) * sizeof(uint64_t));
+ address_offset + GAS_ADDR_OFFSET,
+ sizeof(uint64_t),
+ ACPI_HW_ERROR_FW_CFG_FILE,
+ (ACPI_GHES_ERROR_SOURCE_COUNT + source_id)
+ * sizeof(uint64_t));
/*
* Read Ack Preserve field
@@ -346,11 +354,11 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s,
GArray *hardware_error)
{
/* Create a read-only fw_cfg file for GHES */
- fw_cfg_add_file(s, ACPI_GHES_ERRORS_FW_CFG_FILE, hardware_error->data,
+ fw_cfg_add_file(s, ACPI_HW_ERROR_FW_CFG_FILE, hardware_error->data,
hardware_error->len);
/* Create a read-write fw_cfg file for Address */
- fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL,
+ fw_cfg_add_file_callback(s, ACPI_HW_ERROR_ADDR_FW_CFG_FILE, NULL, NULL,
NULL, &(ags->ghes_addr_le), sizeof(ags->ghes_addr_le), false);
ags->present = true;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 39/48] acpi/ghes: better name the offset of the hardware error firmware
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (37 preceding siblings ...)
2025-01-15 18:10 ` [PULL 38/48] acpi/ghes: rename etc/hardware_error file macros Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 40/48] acpi/ghes: move offset calculus to a separate function Michael S. Tsirkin
` (11 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
The hardware error firmware is where HEST error structures are
stored. Those can be GHESv2, but they can also be other types.
Better name the location of the hardware error.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <ddbb94294bafee998f12fede3ba0b05dae5ee45f.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/ghes.h | 2 +-
hw/acpi/generic_event_device.c | 4 ++--
hw/acpi/ghes.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h
index 21666a4bcc..39619a2457 100644
--- a/include/hw/acpi/ghes.h
+++ b/include/hw/acpi/ghes.h
@@ -65,7 +65,7 @@ enum {
};
typedef struct AcpiGhesState {
- uint64_t ghes_addr_le;
+ uint64_t hw_error_le;
bool present; /* True if GHES is present at all on this board */
} AcpiGhesState;
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index 58540c0aaf..c85d97ca37 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -363,7 +363,7 @@ static const VMStateDescription vmstate_ghes = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
- VMSTATE_UINT64(ghes_addr_le, AcpiGhesState),
+ VMSTATE_UINT64(hw_error_le, AcpiGhesState),
VMSTATE_END_OF_LIST()
},
};
@@ -371,7 +371,7 @@ static const VMStateDescription vmstate_ghes = {
static bool ghes_needed(void *opaque)
{
AcpiGedState *s = opaque;
- return s->ghes_state.ghes_addr_le;
+ return s->ghes_state.hw_error_le;
}
static const VMStateDescription vmstate_ghes_state = {
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 3f94a5542b..983e28505a 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -359,7 +359,7 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s,
/* Create a read-write fw_cfg file for Address */
fw_cfg_add_file_callback(s, ACPI_HW_ERROR_ADDR_FW_CFG_FILE, NULL, NULL,
- NULL, &(ags->ghes_addr_le), sizeof(ags->ghes_addr_le), false);
+ NULL, &(ags->hw_error_le), sizeof(ags->hw_error_le), false);
ags->present = true;
}
@@ -385,7 +385,7 @@ void ghes_record_cper_errors(const void *cper, size_t len,
}
ags = &acpi_ged_state->ghes_state;
- start_addr = le64_to_cpu(ags->ghes_addr_le);
+ start_addr = le64_to_cpu(ags->hw_error_le);
start_addr += source_id * sizeof(uint64_t);
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 40/48] acpi/ghes: move offset calculus to a separate function
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (38 preceding siblings ...)
2025-01-15 18:10 ` [PULL 39/48] acpi/ghes: better name the offset of the hardware error firmware Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 41/48] acpi/ghes: Change ghes fill logic to work with only one source Michael S. Tsirkin
` (10 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Currently, CPER address location is calculated as an offset of
the hardware_errors table. It is also badly named, as the
offset actually used is the address where the CPER data starts,
and not the beginning of the error source.
Move the logic which calculates such offset to a separate
function, in preparation for a patch that will be changing the
logic to calculate it from the HEST table.
While here, properly name the variable which stores the cper
address.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <60fdd1bf379ba1db3099710868802aa49a27febb.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ghes.c | 40 +++++++++++++++++++++++++++++++---------
1 file changed, 31 insertions(+), 9 deletions(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index 983e28505a..ddb576b940 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -364,10 +364,37 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s,
ags->present = true;
}
+static void get_hw_error_offsets(uint64_t ghes_addr,
+ uint64_t *cper_addr,
+ uint64_t *read_ack_register_addr)
+{
+ if (!ghes_addr) {
+ return;
+ }
+
+ /*
+ * non-HEST version supports only one source, so no need to change
+ * the start offset based on the source ID. Also, we can't validate
+ * the source ID, as it is stored inside the HEST table.
+ */
+
+ cpu_physical_memory_read(ghes_addr, cper_addr,
+ sizeof(*cper_addr));
+
+ *cper_addr = le64_to_cpu(*cper_addr);
+
+ /*
+ * As the current version supports only one source, the ack offset is
+ * just sizeof(uint64_t).
+ */
+ *read_ack_register_addr = ghes_addr +
+ ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t);
+}
+
void ghes_record_cper_errors(const void *cper, size_t len,
uint16_t source_id, Error **errp)
{
- uint64_t error_block_addr, read_ack_register_addr, read_ack_register = 0;
+ uint64_t cper_addr = 0, read_ack_register_addr = 0, read_ack_register;
uint64_t start_addr;
AcpiGedState *acpi_ged_state;
AcpiGhesState *ags;
@@ -389,18 +416,13 @@ void ghes_record_cper_errors(const void *cper, size_t len,
start_addr += source_id * sizeof(uint64_t);
- cpu_physical_memory_read(start_addr, &error_block_addr,
- sizeof(error_block_addr));
+ get_hw_error_offsets(start_addr, &cper_addr, &read_ack_register_addr);
- error_block_addr = le64_to_cpu(error_block_addr);
- if (!error_block_addr) {
+ if (!cper_addr) {
error_setg(errp, "can not find Generic Error Status Block");
return;
}
- read_ack_register_addr = start_addr +
- ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t);
-
cpu_physical_memory_read(read_ack_register_addr,
&read_ack_register, sizeof(read_ack_register));
@@ -421,7 +443,7 @@ void ghes_record_cper_errors(const void *cper, size_t len,
&read_ack_register, sizeof(uint64_t));
/* Write the generic error data entry into guest memory */
- cpu_physical_memory_write(error_block_addr, cper, len);
+ cpu_physical_memory_write(cper_addr, cper, len);
return;
}
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 41/48] acpi/ghes: Change ghes fill logic to work with only one source
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (39 preceding siblings ...)
2025-01-15 18:10 ` [PULL 40/48] acpi/ghes: move offset calculus to a separate function Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 42/48] docs: acpi_hest_ghes: fix documentation for CPER size Michael S. Tsirkin
` (9 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Ani Sinha, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Extending to multiple sources require a BIOS pointer to the
beginning of the HEST table, which in turn requires a backward-compatible
code.
So, the current code supports only one source. Ensure that and simplify
the code.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <66bddd42a64c8515ad98b9975d953b4a70ffcc6d.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/ghes.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index ddb576b940..b709c177cd 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -387,15 +387,13 @@ static void get_hw_error_offsets(uint64_t ghes_addr,
* As the current version supports only one source, the ack offset is
* just sizeof(uint64_t).
*/
- *read_ack_register_addr = ghes_addr +
- ACPI_GHES_ERROR_SOURCE_COUNT * sizeof(uint64_t);
+ *read_ack_register_addr = ghes_addr + sizeof(uint64_t);
}
void ghes_record_cper_errors(const void *cper, size_t len,
uint16_t source_id, Error **errp)
{
uint64_t cper_addr = 0, read_ack_register_addr = 0, read_ack_register;
- uint64_t start_addr;
AcpiGedState *acpi_ged_state;
AcpiGhesState *ags;
@@ -412,11 +410,9 @@ void ghes_record_cper_errors(const void *cper, size_t len,
}
ags = &acpi_ged_state->ghes_state;
- start_addr = le64_to_cpu(ags->hw_error_le);
-
- start_addr += source_id * sizeof(uint64_t);
-
- get_hw_error_offsets(start_addr, &cper_addr, &read_ack_register_addr);
+ assert(ACPI_GHES_ERROR_SOURCE_COUNT == 1);
+ get_hw_error_offsets(le64_to_cpu(ags->hw_error_le),
+ &cper_addr, &read_ack_register_addr);
if (!cper_addr) {
error_setg(errp, "can not find Generic Error Status Block");
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 42/48] docs: acpi_hest_ghes: fix documentation for CPER size
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (40 preceding siblings ...)
2025-01-15 18:10 ` [PULL 41/48] acpi/ghes: Change ghes fill logic to work with only one source Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 43/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
` (8 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Mauro Carvalho Chehab, Jonathan Cameron,
Igor Mammedov, Dongjiu Geng, qemu-arm
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
While the spec defines a CPER size of 4KiB for each record,
currently it is set to 1KiB. Fix the documentation and add
a pointer to the macro name there, as this may help to keep
it updated.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <f7e94433bec19a9d6b23ecccc24b5fe3a6f7f52b.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
docs/specs/acpi_hest_ghes.rst | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/docs/specs/acpi_hest_ghes.rst b/docs/specs/acpi_hest_ghes.rst
index 68f1fbe0a4..c3e9f8d9a7 100644
--- a/docs/specs/acpi_hest_ghes.rst
+++ b/docs/specs/acpi_hest_ghes.rst
@@ -67,8 +67,10 @@ Design Details
(3) The address registers table contains N Error Block Address entries
and N Read Ack Register entries. The size for each entry is 8-byte.
The Error Status Data Block table contains N Error Status Data Block
- entries. The size for each entry is 4096(0x1000) bytes. The total size
- for the "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) bytes.
+ entries. The size for each entry is defined at the source code as
+ ACPI_GHES_MAX_RAW_DATA_LENGTH (currently 1024 bytes). The total size
+ for the "etc/hardware_errors" fw_cfg blob is
+ (N * 8 * 2 + N * ACPI_GHES_MAX_RAW_DATA_LENGTH) bytes.
N is the number of the kinds of hardware error sources.
(4) QEMU generates the ACPI linker/loader script for the firmware. The
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 43/48] tests: acpi: whitelist expected blobs
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (41 preceding siblings ...)
2025-01-15 18:10 ` [PULL 42/48] docs: acpi_hest_ghes: fix documentation for CPER size Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 44/48] pci: acpi: Windows 'PCI Label Id' bug workaround Michael S. Tsirkin
` (7 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Igor Mammedov, Ani Sinha
From: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20250115125342.3883374-2-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 40 +++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..085dfa9ff4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,41 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/x86/pc/DSDT",
+"tests/data/acpi/x86/pc/DSDT.acpierst",
+"tests/data/acpi/x86/pc/DSDT.acpihmat",
+"tests/data/acpi/x86/pc/DSDT.bridge",
+"tests/data/acpi/x86/pc/DSDT.cphp",
+"tests/data/acpi/x86/pc/DSDT.dimmpxm",
+"tests/data/acpi/x86/pc/DSDT.hpbridge",
+"tests/data/acpi/x86/pc/DSDT.ipmikcs",
+"tests/data/acpi/x86/pc/DSDT.memhp",
+"tests/data/acpi/x86/pc/DSDT.nohpet",
+"tests/data/acpi/x86/pc/DSDT.numamem",
+"tests/data/acpi/x86/pc/DSDT.roothp",
+"tests/data/acpi/x86/q35/DSDT",
+"tests/data/acpi/x86/q35/DSDT.acpierst",
+"tests/data/acpi/x86/q35/DSDT.acpihmat",
+"tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x",
+"tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator",
+"tests/data/acpi/x86/q35/DSDT.applesmc",
+"tests/data/acpi/x86/q35/DSDT.bridge",
+"tests/data/acpi/x86/q35/DSDT.core-count",
+"tests/data/acpi/x86/q35/DSDT.core-count2",
+"tests/data/acpi/x86/q35/DSDT.cphp",
+"tests/data/acpi/x86/q35/DSDT.cxl",
+"tests/data/acpi/x86/q35/DSDT.dimmpxm",
+"tests/data/acpi/x86/q35/DSDT.ipmibt",
+"tests/data/acpi/x86/q35/DSDT.ipmismbus",
+"tests/data/acpi/x86/q35/DSDT.ivrs",
+"tests/data/acpi/x86/q35/DSDT.memhp",
+"tests/data/acpi/x86/q35/DSDT.mmio64",
+"tests/data/acpi/x86/q35/DSDT.multi-bridge",
+"tests/data/acpi/x86/q35/DSDT.nohpet",
+"tests/data/acpi/x86/q35/DSDT.numamem",
+"tests/data/acpi/x86/q35/DSDT.pvpanic-isa",
+"tests/data/acpi/x86/q35/DSDT.thread-count",
+"tests/data/acpi/x86/q35/DSDT.thread-count2",
+"tests/data/acpi/x86/q35/DSDT.tis.tpm12",
+"tests/data/acpi/x86/q35/DSDT.tis.tpm2",
+"tests/data/acpi/x86/q35/DSDT.type4-count",
+"tests/data/acpi/x86/q35/DSDT.viot",
+"tests/data/acpi/x86/q35/DSDT.xapic",
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 44/48] pci: acpi: Windows 'PCI Label Id' bug workaround
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (42 preceding siblings ...)
2025-01-15 18:10 ` [PULL 43/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 45/48] tests: acpi: update expected blobs Michael S. Tsirkin
` (6 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum
From: Igor Mammedov <imammedo@redhat.com>
Current versions of Windows call _DSM(func=7) regardless
of whether it is supported or not. It leads to NICs having bogus
'PCI Label Id = 0', where none should be set at all.
Also presence of 'PCI Label Id' triggers another Windows bug
on localized versions that leads to hangs. The later bug is fixed
in latest updates for 'Windows Server' but not in consumer
versions of Windows (and there is no plans to fix it
as far as I'm aware).
Given it's easy, implement Microsoft suggested workaround
(return invalid Package) so that affected Windows versions
could boot on QEMU.
This would effectvely remove bogus 'PCI Label Id's on NICs,
but MS teem confirmed that flipping 'PCI Label Id' should not
change 'Network Connection' ennumeration, so it should be safe
for QEMU to change _DSM without any compat code.
Smoke tested with WinXP and WS2022
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/774
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20250115125342.3883374-3-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/acpi-build.c | 33 +++++++++++++++++++++++----------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 733b8f0851..1311a0d4f3 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -654,6 +654,7 @@ static Aml *aml_pci_pdsm(void)
Aml *acpi_index = aml_local(2);
Aml *zero = aml_int(0);
Aml *one = aml_int(1);
+ Aml *not_supp = aml_int(0xFFFFFFFF);
Aml *func = aml_arg(2);
Aml *params = aml_arg(4);
Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
@@ -678,7 +679,7 @@ static Aml *aml_pci_pdsm(void)
*/
ifctx1 = aml_if(aml_lnot(
aml_or(aml_equal(acpi_index, zero),
- aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
+ aml_equal(acpi_index, not_supp), NULL)
));
{
/* have supported functions */
@@ -704,18 +705,30 @@ static Aml *aml_pci_pdsm(void)
{
Aml *pkg = aml_package(2);
- aml_append(pkg, zero);
- /*
- * optional, if not impl. should return null string
- */
- aml_append(pkg, aml_string("%s", ""));
- aml_append(ifctx, aml_store(pkg, ret));
-
aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
+ aml_append(ifctx, aml_store(pkg, ret));
/*
- * update acpi-index to actual value
+ * Windows calls func=7 without checking if it's available,
+ * as workaround Microsoft has suggested to return invalid for func7
+ * Package, so return 2 elements package but only initialize elements
+ * when acpi_index is supported and leave them uninitialized, which
+ * leads elements to being Uninitialized ObjectType and should trip
+ * Windows into discarding result as an unexpected and prevent setting
+ * bogus 'PCI Label' on the device.
*/
- aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
+ ifctx1 = aml_if(aml_lnot(aml_lor(
+ aml_equal(acpi_index, zero), aml_equal(acpi_index, not_supp)
+ )));
+ {
+ aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
+ /*
+ * optional, if not impl. should return null string
+ */
+ aml_append(ifctx1, aml_store(aml_string("%s", ""),
+ aml_index(ret, one)));
+ }
+ aml_append(ifctx, ifctx1);
+
aml_append(ifctx, aml_return(ret));
}
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 45/48] tests: acpi: update expected blobs
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (43 preceding siblings ...)
2025-01-15 18:10 ` [PULL 44/48] pci: acpi: Windows 'PCI Label Id' bug workaround Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 46/48] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr` Michael S. Tsirkin
` (5 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Igor Mammedov, Ani Sinha
From: Igor Mammedov <imammedo@redhat.com>
_DSM function 7 AML should have followig change:
If ((Arg2 == 0x07))
{
- Local0 = Package (0x02)
- {
- Zero,
- ""
- }
Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One]
))
- Local0 [Zero] = Local2
+ Local0 = Package (0x02) {}
+ If (!((Local2 == Zero) || (Local2 == 0xFFFFFFFF)))
+ {
+ Local0 [Zero] = Local2
+ Local0 [One] = ""
+ }
+
Return (Local0)
}
}
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20250115125342.3883374-4-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 40 ------------------
tests/data/acpi/x86/pc/DSDT | Bin 8593 -> 8611 bytes
tests/data/acpi/x86/pc/DSDT.acpierst | Bin 8504 -> 8522 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat | Bin 9918 -> 9936 bytes
tests/data/acpi/x86/pc/DSDT.bridge | Bin 15464 -> 15482 bytes
tests/data/acpi/x86/pc/DSDT.cphp | Bin 9057 -> 9075 bytes
tests/data/acpi/x86/pc/DSDT.dimmpxm | Bin 10247 -> 10265 bytes
tests/data/acpi/x86/pc/DSDT.hpbridge | Bin 8544 -> 8562 bytes
tests/data/acpi/x86/pc/DSDT.ipmikcs | Bin 8665 -> 8683 bytes
tests/data/acpi/x86/pc/DSDT.memhp | Bin 9952 -> 9970 bytes
tests/data/acpi/x86/pc/DSDT.nohpet | Bin 8451 -> 8469 bytes
tests/data/acpi/x86/pc/DSDT.numamem | Bin 8599 -> 8617 bytes
tests/data/acpi/x86/pc/DSDT.roothp | Bin 12386 -> 12404 bytes
tests/data/acpi/x86/q35/DSDT | Bin 8422 -> 8440 bytes
tests/data/acpi/x86/q35/DSDT.acpierst | Bin 8439 -> 8457 bytes
tests/data/acpi/x86/q35/DSDT.acpihmat | Bin 9747 -> 9765 bytes
.../data/acpi/x86/q35/DSDT.acpihmat-generic-x | Bin 12632 -> 12650 bytes
.../acpi/x86/q35/DSDT.acpihmat-noinitiator | Bin 8701 -> 8719 bytes
tests/data/acpi/x86/q35/DSDT.applesmc | Bin 8468 -> 8486 bytes
tests/data/acpi/x86/q35/DSDT.bridge | Bin 12035 -> 12053 bytes
tests/data/acpi/x86/q35/DSDT.core-count | Bin 12980 -> 12998 bytes
tests/data/acpi/x86/q35/DSDT.core-count2 | Bin 33837 -> 33855 bytes
tests/data/acpi/x86/q35/DSDT.cphp | Bin 8886 -> 8904 bytes
tests/data/acpi/x86/q35/DSDT.cxl | Bin 13213 -> 13231 bytes
tests/data/acpi/x86/q35/DSDT.dimmpxm | Bin 10076 -> 10094 bytes
tests/data/acpi/x86/q35/DSDT.ipmibt | Bin 8497 -> 8515 bytes
tests/data/acpi/x86/q35/DSDT.ipmismbus | Bin 8510 -> 8528 bytes
tests/data/acpi/x86/q35/DSDT.ivrs | Bin 8439 -> 8457 bytes
tests/data/acpi/x86/q35/DSDT.memhp | Bin 9781 -> 9799 bytes
tests/data/acpi/x86/q35/DSDT.mmio64 | Bin 9552 -> 9570 bytes
tests/data/acpi/x86/q35/DSDT.multi-bridge | Bin 13275 -> 13293 bytes
tests/data/acpi/x86/q35/DSDT.nohpet | Bin 8280 -> 8298 bytes
tests/data/acpi/x86/q35/DSDT.numamem | Bin 8428 -> 8446 bytes
tests/data/acpi/x86/q35/DSDT.pvpanic-isa | Bin 8523 -> 8541 bytes
tests/data/acpi/x86/q35/DSDT.thread-count | Bin 12980 -> 12998 bytes
tests/data/acpi/x86/q35/DSDT.thread-count2 | Bin 33837 -> 33855 bytes
tests/data/acpi/x86/q35/DSDT.tis.tpm12 | Bin 9028 -> 9046 bytes
tests/data/acpi/x86/q35/DSDT.tis.tpm2 | Bin 9054 -> 9072 bytes
tests/data/acpi/x86/q35/DSDT.type4-count | Bin 18656 -> 18674 bytes
tests/data/acpi/x86/q35/DSDT.viot | Bin 14679 -> 14697 bytes
tests/data/acpi/x86/q35/DSDT.xapic | Bin 35785 -> 35803 bytes
41 files changed, 40 deletions(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 085dfa9ff4..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,41 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/x86/pc/DSDT",
-"tests/data/acpi/x86/pc/DSDT.acpierst",
-"tests/data/acpi/x86/pc/DSDT.acpihmat",
-"tests/data/acpi/x86/pc/DSDT.bridge",
-"tests/data/acpi/x86/pc/DSDT.cphp",
-"tests/data/acpi/x86/pc/DSDT.dimmpxm",
-"tests/data/acpi/x86/pc/DSDT.hpbridge",
-"tests/data/acpi/x86/pc/DSDT.ipmikcs",
-"tests/data/acpi/x86/pc/DSDT.memhp",
-"tests/data/acpi/x86/pc/DSDT.nohpet",
-"tests/data/acpi/x86/pc/DSDT.numamem",
-"tests/data/acpi/x86/pc/DSDT.roothp",
-"tests/data/acpi/x86/q35/DSDT",
-"tests/data/acpi/x86/q35/DSDT.acpierst",
-"tests/data/acpi/x86/q35/DSDT.acpihmat",
-"tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x",
-"tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator",
-"tests/data/acpi/x86/q35/DSDT.applesmc",
-"tests/data/acpi/x86/q35/DSDT.bridge",
-"tests/data/acpi/x86/q35/DSDT.core-count",
-"tests/data/acpi/x86/q35/DSDT.core-count2",
-"tests/data/acpi/x86/q35/DSDT.cphp",
-"tests/data/acpi/x86/q35/DSDT.cxl",
-"tests/data/acpi/x86/q35/DSDT.dimmpxm",
-"tests/data/acpi/x86/q35/DSDT.ipmibt",
-"tests/data/acpi/x86/q35/DSDT.ipmismbus",
-"tests/data/acpi/x86/q35/DSDT.ivrs",
-"tests/data/acpi/x86/q35/DSDT.memhp",
-"tests/data/acpi/x86/q35/DSDT.mmio64",
-"tests/data/acpi/x86/q35/DSDT.multi-bridge",
-"tests/data/acpi/x86/q35/DSDT.nohpet",
-"tests/data/acpi/x86/q35/DSDT.numamem",
-"tests/data/acpi/x86/q35/DSDT.pvpanic-isa",
-"tests/data/acpi/x86/q35/DSDT.thread-count",
-"tests/data/acpi/x86/q35/DSDT.thread-count2",
-"tests/data/acpi/x86/q35/DSDT.tis.tpm12",
-"tests/data/acpi/x86/q35/DSDT.tis.tpm2",
-"tests/data/acpi/x86/q35/DSDT.type4-count",
-"tests/data/acpi/x86/q35/DSDT.viot",
-"tests/data/acpi/x86/q35/DSDT.xapic",
diff --git a/tests/data/acpi/x86/pc/DSDT b/tests/data/acpi/x86/pc/DSDT
index 60d50b088a362556fd54395cb15364d6c0936be5..4beb5194b84a711fcb52e3e52cc2096497d18442 100644
GIT binary patch
delta 89
zcmV-f0H*(uL!(0qL{mgmqagqQ0q~Iu-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXh>8L>3-R
delta 71
zcmZ4NJkgoUCD<ioq9OwWqy0p#2TVR96W{D$a^jr4j4@kDb#fLLdw~!u69X?pLV=^F
bOGI-=4g*7TM-C%HQbAHj0>frkrZ{;3=vWj@
diff --git a/tests/data/acpi/x86/pc/DSDT.acpierst b/tests/data/acpi/x86/pc/DSDT.acpierst
index 4c434c25c0b1602f22128e352781df498fa69ddf..abda6863b64c5dc8ba5aba1a286cbfa76772a1e4 100644
GIT binary patch
delta 89
zcmV-f0H*)ALdrr4L{mgmN+AFM0XUHg-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXe!43(g%c
delta 71
zcmX@*w8M$ZCD<jzLXm-iv3(-f112AliEnl=IdM*2#+a?7IysAry+DYSiGi0Pp}^78
bC8D__hk>EFBZrY8sUWE%fnl>N6RSJ`_UaTb
diff --git a/tests/data/acpi/x86/pc/DSDT.acpihmat b/tests/data/acpi/x86/pc/DSDT.acpihmat
index 61b7d5caa55c44dbf69d649110c6b14bb4c3fdf5..d081db26d7ba504b3344fad130d5812419291ac0 100644
GIT binary patch
delta 89
zcmV-f0H*)GP0&pWL{mgm&?W!?0j-e=-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXjewW-A`t
delta 71
zcmccMyU&-)CD<iopBe)L<DZFK514#JCcfFh<it678DqAR>f|gg_5vYRCI()HgaSuT
bmx$($90rEwjvPjYq=KZ51cuG7Ox-E~Jn|LX
diff --git a/tests/data/acpi/x86/pc/DSDT.bridge b/tests/data/acpi/x86/pc/DSDT.bridge
index d43e148bed19160f39d88ccf3364544150a3f87f..e16897dc5f0fbb3f7b4de8db913884046246cc3b 100644
GIT binary patch
delta 89
zcmV-f0H*)wc=~t>L{mgmdOQFC0sfH+-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXga_qf{SP
delta 71
zcmexW@uGsuCD<h-!-j!@(RU)(112AliEnl=IdM*2#+a?7IysAry+DYSiGi0Pp}^78
bC8D__hk>EFBZrY8sUWE%fnl>Nlc^N|GxZf$
diff --git a/tests/data/acpi/x86/pc/DSDT.cphp b/tests/data/acpi/x86/pc/DSDT.cphp
index 9fda0b56638e02097e58dd4536c9c5955986e88e..e95711cd9cde5d50b841b701ae0fed5a4b15e872 100644
GIT binary patch
delta 89
zcmV-f0H*)pM)O7rL{mgmb0Yu%0b`L0-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXgFlMG+nf
delta 71
zcmezD_Rx*XCD<h-QJH~(annSu2TVR96W{D$a^jr4j4@kDb#fLLdw~!u69X?pLV=^F
bOGI-=4g*7TM-C%HQbAHj0>frkCOt&}Bit1V
diff --git a/tests/data/acpi/x86/pc/DSDT.dimmpxm b/tests/data/acpi/x86/pc/DSDT.dimmpxm
index 5b6471c8db9003b39bf5e20af34061f3e71cdbd5..90ba66b9164f9a958d5a3c4371b1eec03e922828 100644
GIT binary patch
delta 89
zcmV-f0H*(kP?=B)L{mgm87Ke%0T7W2-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXm5l+*loK
delta 71
zcmbOk&>q0$66_MfuED^-7(bEg0h5oX&boH!>hW6V}kot(wRULeHE#K6mtP~hn4
b64Bg|!@$tok;BN4RFKq>z_8hs>53`<(lZon
diff --git a/tests/data/acpi/x86/pc/DSDT.hpbridge b/tests/data/acpi/x86/pc/DSDT.hpbridge
index 67fe28699fbb261cfc7a52b2291f9965ab93c6a8..0eafe5fbf3d73719c9c3e6e26371863bfb44ed2f 100644
GIT binary patch
delta 89
zcmV-f0H*)oLh?ciL{mgmav=Z!0VI(M-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXgCiE<zo<
delta 71
zcmez5^uUSBCD<h-L6L!hv3Mfa112AliEnl=IdM*2#+a?7IysAry+DYSiGi0Pp}^78
bC8D__hk>EFBZrY8sUWE%fnl>Nlde1f5@i&-
diff --git a/tests/data/acpi/x86/pc/DSDT.ipmikcs b/tests/data/acpi/x86/pc/DSDT.ipmikcs
index 9b2e81a7bcefb5c0e2dfbd2bbc5b6ea501f86306..8d465f027772f9c59b0c328c1a099e374a6d2a90 100644
GIT binary patch
delta 89
zcmV-f0H*)hL+e8dL{mgm>mdLD0c?>9-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXka`W%?fJ
delta 71
zcmaFueAAiBCD<k8rXm9a<L-%E514#JCcfFh<it678DqAR>f|gg_5vYRCI()HgaSuT
bmx$($90rEwjvPjYq=KZ51cuG7Ov~f}J!2K=
diff --git a/tests/data/acpi/x86/pc/DSDT.memhp b/tests/data/acpi/x86/pc/DSDT.memhp
index 9c66ccf150af1622d1b788a1ae04a6e5136cff9e..e3b49757cb7abd7536ee89a6824967d2cb2485cf 100644
GIT binary patch
delta 89
zcmV-f0H*)oP4Z0&L{mgm@+JTP0mP9C-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXkw7k1QX1
delta 71
zcmez5`@omWCD<k8ff@q?qwqwo2TVR96W{D$a^jr4j4@kDb#fLLdw~!u69X?pLV=^F
bOGI-=4g*7TM-C%HQbAHj0>frkrnM>nBq<ep
diff --git a/tests/data/acpi/x86/pc/DSDT.nohpet b/tests/data/acpi/x86/pc/DSDT.nohpet
index 28dbd8d8949d1421da9312cf0440d7ae3b64916e..9e772c1316d0ea07c51717466c4c7e383553f345 100644
GIT binary patch
delta 89
zcmV-f0H*(gLX|=aL{mgm6(Ils0lAS1-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXl^a{vRFN
delta 71
zcmbR0)a=CN66_MftjNH?$T5-Y0h5oX&boH!>hW6V}kot(wRULeHE#K6mtP~hn4
b64Bg|!@$tok;BN4RFKq>z_8hs>4F>pvSt(8
diff --git a/tests/data/acpi/x86/pc/DSDT.numamem b/tests/data/acpi/x86/pc/DSDT.numamem
index e256bbce790152f045247db631d9f1da81f90499..9bfbfc28213713c208dfc38a85abb46fb190871d 100644
GIT binary patch
delta 89
zcmV-f0H*(!L#aawL{mgmsUZLW0eq1P-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXi8EC?*~8
delta 71
zcmZ4KJl&bgCD<iox*`Ju<LQZ9514#JCcfFh<it678DqAR>f|gg_5vYRCI()HgaSuT
bmx$($90rEwjvPjYq=KZ51cuG7OeyjJ3|kcO
diff --git a/tests/data/acpi/x86/pc/DSDT.roothp b/tests/data/acpi/x86/pc/DSDT.roothp
index 0557810ddc18dc280d039163c72b25428a2486c1..efbee6d8aa5c62ff4fcb83e6c5cff59542977850 100644
GIT binary patch
delta 89
zcmV-f0H*)qVDw-LL{mgmbT9w_0eq1P-~vt+k?gnvL<*Cp0c$ijlWGbFa6w5#Sc8ac
v004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;GXgIzV<H}P
delta 71
zcmey8@F;=HCD<h-$$)`@@$^Kl2TVR96W{D$a^jr4j4@kDb#fLLdw~!u69X?pLV=^F
bOGI-=4g*7TM-C%HQbAHj0>frkCVf2sJ7X1f
diff --git a/tests/data/acpi/x86/q35/DSDT b/tests/data/acpi/x86/q35/DSDT
index 51ad37a351bffae8fbc9ba17f72c25ef61822f59..e5e8d1e041e20e1b3ee56a5c93fe3d6ebd721ee6 100644
GIT binary patch
delta 91
zcmV-h0HpusLHI!mL{mgm_#glP0lu*cp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1@*Q=CAJ6~*
delta 73
zcmez2_{@>ZCD<k8nF0d?BkxA8g^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaK_KSpX366wv?x
diff --git a/tests/data/acpi/x86/q35/DSDT.acpierst b/tests/data/acpi/x86/q35/DSDT.acpierst
index dbd4f858354df0f4c050fd0b914581154f340ee8..072a3fe2cd17dfe06658dfd82588f69787810114 100644
GIT binary patch
delta 91
zcmV-h0Hpu-L5V^NL{mgm2_XOg0bQ{Qp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ110L!89X0>}
delta 73
zcmeBl`tHc(66_N4U4emtaqUK~g^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaECr8~`1R6gL0>
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat b/tests/data/acpi/x86/q35/DSDT.acpihmat
index 952752e30e9dfc9e2085e8fceaa0740dda6db89c..2a4f2fc1d5c5649673353186e67ff5b5e59e8d53 100644
GIT binary patch
delta 91
zcmV-h0HptuOr=Z;L{mgmB_;p>0eZ0tp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1A0z7h9by0g
delta 73
zcmZ4LGuemBCD<iISdD>!@#IFXg^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaIwKG63GX6Jr1X
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x b/tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x
index e95258cbd8681103a642f8973bd1ac9ef229cff7..7911c058bba5005d318b8db8d6da5c1ee381b0f1 100644
GIT binary patch
delta 91
zcmV-h0HpueV(MZFL{mgmYB2x+0Uxmnp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1WG*SE9$f$c
delta 73
zcmaErbR&t&CD<h-!jOT1F>fQ+LPjPZk;!WrcQ83|PEKdaR#Kgu#l>DA#LC3L%aBmu
d=;;#C+>yh;(A<&3$dFW!)RDljnT<I`4*(Hf6kY%T
diff --git a/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator b/tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
index ba2a7d0004be7cd7220716dc7e8594be87197b98..580b4a456a20fc0cc0a832eaf74193b46d8ae8b1 100644
GIT binary patch
delta 91
zcmV-h0Hpu@LytrXL{mgm4<Y~n0W`4+p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ12_NN+9V-9;
delta 73
zcmeBo`RmN(66_N4SCN5%v1KFILPjPZk;!WrcQ83|PEKdaR#Kgu#l>DA#LC3L%aBmu
d=;;#C+>yh;(A<&3$dFW!)RDljnT?rK9sn9)6f6J$
diff --git a/tests/data/acpi/x86/q35/DSDT.applesmc b/tests/data/acpi/x86/q35/DSDT.applesmc
index b6cb840953ea539092f601e08b7122fc999b3e1b..5e8220e38d6f88b103f6eb3eb7c78dfa466882dc 100644
GIT binary patch
delta 91
zcmV-h0HptvLZ(6rL{mgmCLsU-0j;qLp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1ARhA09eV%(
delta 73
zcmZ4HG{uR_CD<iIM3I4k@y|xCg^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaIvl9025j6MO&w
diff --git a/tests/data/acpi/x86/q35/DSDT.bridge b/tests/data/acpi/x86/q35/DSDT.bridge
index 1939fda2507cde6fcb6f7a093897f9bd2cb987ef..ee039453af1071e00a81ee7b37cf8f417f524257 100644
GIT binary patch
delta 91
zcmV-h0HpteUX@-7L{mgm6)yk)0okz%p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ14=e_S9k&1g
delta 73
zcmbOl*Br;?66_Mftk1x}sIif2AtRHI$mF$*JD8j}C#N%IE2&P-;$kllVr63BWk@J+
d^mK`6?#N+aXzs{iWJoGV>PTSN%*M>G0|2<Y61V^W
diff --git a/tests/data/acpi/x86/q35/DSDT.core-count b/tests/data/acpi/x86/q35/DSDT.core-count
index 41c0832ab5041ff5361598813ec28fe7442b191b..7ebfceeb66460d0ad98471924ce224b7153e87ef 100644
GIT binary patch
delta 91
zcmV-h0Hpu4WyWO+L{mgm#xei^0XDG;p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1z%Mu29_#=B
delta 73
zcmX?>x+Rs%CD<ioixC3@W9vq)g^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaK^(eE=K{6zu>2
diff --git a/tests/data/acpi/x86/q35/DSDT.core-count2 b/tests/data/acpi/x86/q35/DSDT.core-count2
index 153b45f0f7443d25cecc2a752fb6dbd921160e78..d0394558a1faa0b4ba43abab66d474d96b477ff3 100644
GIT binary patch
delta 93
zcmV-j0HXh`hyuTe0t!S^L{vY70004pu?nF90!|f^tpT_KL<*B<0&6rklWGbFa6w5#
zSc8ac004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;^a447R<a)t
delta 75
zcmdnr!L+u6iOVI}B}BJ{fr0VbMy`d7Og<u$*D~&4a^jqv&XldBIysAry+DYSiGi0P
fp}^78C8D__hk>EFBZrY8sUWE%fnhTnvt=UyG{+SX
diff --git a/tests/data/acpi/x86/q35/DSDT.cphp b/tests/data/acpi/x86/q35/DSDT.cphp
index 231bc23d932e832ffa12dd253bcf54245b5ef88f..a055c2e7d3c4f5a00a03be20fd73227e322283a4 100644
GIT binary patch
delta 91
zcmV-h0Hpu6MaV@8L{mgm$RYp$0Wq-(p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1!XF(89*+P3
delta 73
zcmX@%y3Li#CD<ion-T*9W5Y(Sg^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaK_Ec>o5=6p#P_
diff --git a/tests/data/acpi/x86/q35/DSDT.cxl b/tests/data/acpi/x86/q35/DSDT.cxl
index 0f1ccdfcc3ffbf151c172015cc4bf18bc4ead218..20843549f54af1cb0e6017c4cfff7463318d9eb7 100644
GIT binary patch
delta 91
zcmV-h0Hpt&XRl`pL{mgmuQLDu0rIg5p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1sW4h(A5s7S
delta 73
zcmZ3VJ~y4qCD<iot}z1xqvJ-dg^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaK_t0|5Ha6jJ~I
diff --git a/tests/data/acpi/x86/q35/DSDT.dimmpxm b/tests/data/acpi/x86/q35/DSDT.dimmpxm
index eb5b6e9f52107d9c95e38e94a67a6b5001beafc1..664e926e90765550136242f7e3e0bdc7719c1853 100644
GIT binary patch
delta 91
zcmV-h0HpuiPVP<$L{mgmZYKZ$0p76+p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1Xe3r19`FDF
delta 73
zcmaFocgK&*CD<h-MxB9yQFkNPLPjPZk;!WrcQ83|PEKdaR#Kgu#l>DA#LC3L%aBmu
d=;;#C+>yh;(A<&3$dFW!)RDljnT<I^1pxR26Y&55
diff --git a/tests/data/acpi/x86/q35/DSDT.ipmibt b/tests/data/acpi/x86/q35/DSDT.ipmibt
index 524fc9f4ee09fd7a5bec62818fd87b6ec300dee8..4066a76d26aa380dfbecc58aa3f83ab5db2baadb 100644
GIT binary patch
delta 91
zcmV-h0Hpu1Lc>A|L{mgmLm>bF0r9a4p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1Jsu@F9y0&{
delta 73
zcmX@?w9$#nCD<jzP?3Rw(P1OkLPjPZk;!WrcQ83|PEKdaR#Kgu#l>DA#LC3L%aBmu
d=;;#C+>yh;(A<&3$dFW!)RDljnT^?24gk>i6Epw-
diff --git a/tests/data/acpi/x86/q35/DSDT.ipmismbus b/tests/data/acpi/x86/q35/DSDT.ipmismbus
index d04d215a1d0fbc77739084d100a35af47a1c1a62..6d0b6b95c2a9fd01befc37b26650781ee1562e2a 100644
GIT binary patch
delta 91
zcmV-h0HpuELeN4AL{mgmP$2*S0b;QVp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1N*)KE9oPT>
delta 73
zcmccMw9kplCD<jzPLY9uapOj=g^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaIv)902vK6WIU&
diff --git a/tests/data/acpi/x86/q35/DSDT.ivrs b/tests/data/acpi/x86/q35/DSDT.ivrs
index dbd4f858354df0f4c050fd0b914581154f340ee8..072a3fe2cd17dfe06658dfd82588f69787810114 100644
GIT binary patch
delta 91
zcmV-h0Hpu-L5V^NL{mgm2_XOg0bQ{Qp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ110L!89X0>}
delta 73
zcmeBl`tHc(66_N4U4emtaqUK~g^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaECr8~`1R6gL0>
diff --git a/tests/data/acpi/x86/q35/DSDT.memhp b/tests/data/acpi/x86/q35/DSDT.memhp
index f73ade9bf6e4545f9912ed654a282884a54cec79..4f2f9bcfceff076490cc49b8286380295a340004 100644
GIT binary patch
delta 91
zcmV-h0Hpu5Ovg+LL{mgmM<xIO0g<r^p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1K_e9h9svLV
delta 73
zcmX@^v(<;oCD<jzRE>dw@xex}g^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaIv`G64VU6aoMM
diff --git a/tests/data/acpi/x86/q35/DSDT.mmio64 b/tests/data/acpi/x86/q35/DSDT.mmio64
index f0ddb4c83cdc9afdf4f289a66ed6bf0d630fd623..0fb6aab16f1bd79f3c0790cc9f644f7e52ac37b1 100644
GIT binary patch
delta 91
zcmV-h0HpuWO5#ciL{mgmVkH0o0aCFFp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1Tp}Dc9w-0+
delta 73
zcmaFlb-|0vCD<h-K$U@kap6X;g^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaGY^5&#B26e$1z
diff --git a/tests/data/acpi/x86/q35/DSDT.multi-bridge b/tests/data/acpi/x86/q35/DSDT.multi-bridge
index 3ad19e3f5e480db1c449b838c83833f7665186cd..f6afa6d96d2525d512cc46f17439f7a49962b730 100644
GIT binary patch
delta 91
zcmV-h0HpuhXYFSSL{mgm?K1!X0n@Pxp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1=P;20AS(a>
delta 73
zcmaExemkAZCD<k8wlM<(qtZsMg^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaK`B0{|wL6)XS%
diff --git a/tests/data/acpi/x86/q35/DSDT.nohpet b/tests/data/acpi/x86/q35/DSDT.nohpet
index c089b5877a0f4d808abd4d8d9396ee7d2a9a78e5..99ad629c9171ff6ab346d6b4c519e77ca23e5b1c 100644
GIT binary patch
delta 91
zcmV-h0HpueK<YpWL{mgmY9Igr0f(^)p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1WF0Hn9$x?e
delta 73
zcmaFmaKnMiCD<h-LV<yS@!CeNg^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaGY?EC3QZ6kq@V
diff --git a/tests/data/acpi/x86/q35/DSDT.numamem b/tests/data/acpi/x86/q35/DSDT.numamem
index 2867f5b44498d788fc0effd0bf616317821be88e..fd1d8a79d3d9b071c8796e5e99b76698a9a8d29c 100644
GIT binary patch
delta 91
zcmV-h0HpuyLH<DsL{mgm{vZGV0ZOq7p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1_#If%A9Mf!
delta 73
zcmez8_{NdTCD<k8jRFG$<IIg*3mKVwL?*9g+`;6;IXRsvTS;|t78iSg5GxY{FGE6s
dqo+$mb4LyXLvu$CBSTU_Qbz*AW;W&@vH&(A6?Fgr
diff --git a/tests/data/acpi/x86/q35/DSDT.pvpanic-isa b/tests/data/acpi/x86/q35/DSDT.pvpanic-isa
index 02cc07f010f880684216ba8925c8f3f55cfd80aa..89032fa0290f496be0c06c6382586541aa1118a8 100644
GIT binary patch
delta 91
zcmV-h0HpuRLft|NL{mgmT_FGf0dTPjp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1R~{KW9vT1u
delta 73
zcmccXblQo_CD<jzTakf*asNiHg^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaGZb8~_8K6dM2l
diff --git a/tests/data/acpi/x86/q35/DSDT.thread-count b/tests/data/acpi/x86/q35/DSDT.thread-count
index 41c0832ab5041ff5361598813ec28fe7442b191b..7ebfceeb66460d0ad98471924ce224b7153e87ef 100644
GIT binary patch
delta 91
zcmV-h0Hpu4WyWO+L{mgm#xei^0XDG;p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1z%Mu29_#=B
delta 73
zcmX?>x+Rs%CD<ioixC3@W9vq)g^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaK^(eE=K{6zu>2
diff --git a/tests/data/acpi/x86/q35/DSDT.thread-count2 b/tests/data/acpi/x86/q35/DSDT.thread-count2
index 153b45f0f7443d25cecc2a752fb6dbd921160e78..d0394558a1faa0b4ba43abab66d474d96b477ff3 100644
GIT binary patch
delta 93
zcmV-j0HXh`hyuTe0t!S^L{vY70004pu?nF90!|f^tpT_KL<*B<0&6rklWGbFa6w5#
zSc8ac004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;^a447R<a)t
delta 75
zcmdnr!L+u6iOVI}B}BJ{fr0VbMy`d7Og<u$*D~&4a^jqv&XldBIysAry+DYSiGi0P
fp}^78C8D__hk>EFBZrY8sUWE%fnhTnvt=UyG{+SX
diff --git a/tests/data/acpi/x86/q35/DSDT.tis.tpm12 b/tests/data/acpi/x86/q35/DSDT.tis.tpm12
index d0330d26a54b89c02a17b06ef5f55c72e28e406e..f2ed40ca70cb13e733e39f4bad756be8688e01fe 100644
GIT binary patch
delta 91
zcmV-h0HpuKM%G3OL{mgmRwDoa0q(I1p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1P#`;29*6({
delta 73
zcmccScEpX#CD<jzMVWzt(RL%(LPjPZk;!WrcQ83|PEKdaR#Kgu#l>DA#LC3L%aBmu
d=;;#C+>yh;(A<&3$dFW!)RDljnT<I>0RZBZ6Nvx-
diff --git a/tests/data/acpi/x86/q35/DSDT.tis.tpm2 b/tests/data/acpi/x86/q35/DSDT.tis.tpm2
index b05563deedc65df50f35b2399862d9ee8d4d1e0e..5c975d2162d0bfee5a3a089e79b5ba038f82b7ef 100644
GIT binary patch
delta 91
zcmV-h0HpukM({=oL{mgma3cT!0jRMGp#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1Y9K)v9;yHU
delta 73
zcmez1cF&E=CD<h-PMLv$@%u)ug^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaGZ30stb_6srIL
diff --git a/tests/data/acpi/x86/q35/DSDT.type4-count b/tests/data/acpi/x86/q35/DSDT.type4-count
index 00807e7fd4d758bc2ab9c69ac8869cf6864399f7..3194a82b8b4f66aff1ecf7d2d60b4890181fc600 100644
GIT binary patch
delta 93
zcmV-j0HXikkpc3N0SZJ@L{#!f0003~u?nF90!|f^tpT_KL<*B<0&6rklWGbFa6w5#
zSc8ac004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;^aAWfn6V%~
delta 75
zcmV-R0JQ(|kpbY50SZJ@L{#8N0004^u?nF90!$Q>tpT_KLJ5;+0&5~AlWGbFa1sRq
h01W_Oa6w5#Sc8ac004uCYykjbaAJsH0J8=I>_utB7C-<1
diff --git a/tests/data/acpi/x86/q35/DSDT.viot b/tests/data/acpi/x86/q35/DSDT.viot
index c3d83e67660ee3fd59f6fae6242270bed4a567f1..129d43e1e561be3fd7cd71406829ab81d0a8aba0 100644
GIT binary patch
delta 91
zcmV-h0Hpuda_MpkL{mgmX*mD@0g$l@p#cI;6_c$2xB^59lV<{JG&hrK3I}jONkmwK
xh-?4=gNSSa0Ag?w0s>&58j_KdVgQq34FCWC|8Qc6U;qGc4FHH>0kiZ1V>Vb!9{K<P
delta 73
zcmaD^biIhnCD<h-+>(KT@%~1xg^Wx-B9qrL?qG7_oSe>-t)x0Ri;KNLh?R+fmm#6R
d(bFZOxg&>xp}8Z6ks+xdsUv}5GaGZV82~kR6#D=G
diff --git a/tests/data/acpi/x86/q35/DSDT.xapic b/tests/data/acpi/x86/q35/DSDT.xapic
index 227d421f16ed1824a87e8a91da734828f8b48cbf..b37ab591110d1c8201575ad6bba83449d7b90b21 100644
GIT binary patch
delta 93
zcmV-j0HXiNmjc_D0t!S^L{!_00004lu?nF90!|f^tpT_KL<*B<0&6rklWGbFa6w5#
zSc8ac004uCYykjba1sInV4xb3k&|KolVS}2|NsARVu)Y>0B{Weh+qM;^a9n0sf!?|
delta 75
zcmV-R0JQ(xmjcO`0t!S^L{!O(0005fu?nF90!$Q>tpT_KLJ5;+0&5~AlWGbFa1sRq
h01W_Oa6w5#Sc8ac004uCYykjbaAJsH0J8=I)rfXx7N`IK
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 46/48] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (44 preceding siblings ...)
2025-01-15 18:10 ` [PULL 45/48] tests: acpi: update expected blobs Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 47/48] vhost: Add stubs for the migration state transfer interface Michael S. Tsirkin
` (4 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Li Zhijian, Jonathan Cameron, Fan Ni
From: Li Zhijian <lizhijian@fujitsu.com>
This assertion always happens when we sanitize the CXL memory device.
$ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
It is incorrect to register an MSIX number beyond the device's capability.
Increase the device's MSIX number to cover the mailbox msix number(9).
Fixes: 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background completion")
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Message-Id: <20250115075834.167504-1-lizhijian@fujitsu.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/mem/cxl_type3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index bd7652740f..0ae1704a34 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -843,7 +843,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
ComponentRegisters *regs = &cxl_cstate->crb;
MemoryRegion *mr = ®s->component_registers;
uint8_t *pci_conf = pci_dev->config;
- unsigned short msix_num = 6;
+ unsigned short msix_num = 10;
int i, rc;
uint16_t count;
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 47/48] vhost: Add stubs for the migration state transfer interface
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (45 preceding siblings ...)
2025-01-15 18:10 ` [PULL 46/48] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr` Michael S. Tsirkin
@ 2025-01-15 18:10 ` Michael S. Tsirkin
2025-01-15 18:11 ` [PULL 48/48] virtio-net: vhost-user: Implement internal migration Michael S. Tsirkin
` (3 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Laurent Vivier, Hanna Czenczek
From: Laurent Vivier <lvivier@redhat.com>
Migration state transfer interface is only used by vhost-user-fs,
so the interface needs to be defined only when vhost is built.
But I need to use this interface with virtio-net and vhost is not always
enabled, and to avoid undefined reference error during build, define stub
functions for vhost_supports_device_state(), vhost_save_backend_state() and
vhost_load_backend_state().
Cc: Hanna Czenczek <hreitz@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <20250115135044.799698-2-lvivier@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/virtio/vhost.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index 461c168c37..a9469d50bc 100644
--- a/include/hw/virtio/vhost.h
+++ b/include/hw/virtio/vhost.h
@@ -365,7 +365,14 @@ static inline int vhost_reset_device(struct vhost_dev *hdev)
* Returns true if the device supports these commands, and false if it
* does not.
*/
+#ifdef CONFIG_VHOST
bool vhost_supports_device_state(struct vhost_dev *dev);
+#else
+static inline bool vhost_supports_device_state(struct vhost_dev *dev)
+{
+ return false;
+}
+#endif
/**
* vhost_set_device_state_fd(): Begin transfer of internal state from/to
@@ -448,7 +455,15 @@ int vhost_check_device_state(struct vhost_dev *dev, Error **errp);
*
* Returns 0 on success, and -errno otherwise.
*/
+#ifdef CONFIG_VHOST
int vhost_save_backend_state(struct vhost_dev *dev, QEMUFile *f, Error **errp);
+#else
+static inline int vhost_save_backend_state(struct vhost_dev *dev, QEMUFile *f,
+ Error **errp)
+{
+ return -ENOSYS;
+}
+#endif
/**
* vhost_load_backend_state(): High-level function to load a vhost
@@ -465,6 +480,14 @@ int vhost_save_backend_state(struct vhost_dev *dev, QEMUFile *f, Error **errp);
*
* Returns 0 on success, and -errno otherwise.
*/
+#ifdef CONFIG_VHOST
int vhost_load_backend_state(struct vhost_dev *dev, QEMUFile *f, Error **errp);
+#else
+static inline int vhost_load_backend_state(struct vhost_dev *dev, QEMUFile *f,
+ Error **errp)
+{
+ return -ENOSYS;
+}
+#endif
#endif
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PULL 48/48] virtio-net: vhost-user: Implement internal migration
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (46 preceding siblings ...)
2025-01-15 18:10 ` [PULL 47/48] vhost: Add stubs for the migration state transfer interface Michael S. Tsirkin
@ 2025-01-15 18:11 ` Michael S. Tsirkin
2025-01-15 18:15 ` [PULL 00/48] virtio,pc,pci: features, fixes, cleanups David Woodhouse
` (2 subsequent siblings)
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 18:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Laurent Vivier, Hanna Czenczek, Jason Wang
From: Laurent Vivier <lvivier@redhat.com>
Add support of VHOST_USER_PROTOCOL_F_DEVICE_STATE in virtio-net
with vhost-user backend.
Cc: Hanna Czenczek <hreitz@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <20250115135044.799698-3-lvivier@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/net/virtio-net.c | 135 ++++++++++++++++++++++++++++++++++++--------
1 file changed, 112 insertions(+), 23 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 06f096abf6..85e14b788c 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -3337,6 +3337,117 @@ static const VMStateDescription vmstate_virtio_net_rss = {
},
};
+static struct vhost_dev *virtio_net_get_vhost(VirtIODevice *vdev)
+{
+ VirtIONet *n = VIRTIO_NET(vdev);
+ NetClientState *nc;
+ struct vhost_net *net;
+
+ if (!n->nic) {
+ return NULL;
+ }
+
+ nc = qemu_get_queue(n->nic);
+ if (!nc) {
+ return NULL;
+ }
+
+ net = get_vhost_net(nc->peer);
+ if (!net) {
+ return NULL;
+ }
+
+ return &net->dev;
+}
+
+static int vhost_user_net_save_state(QEMUFile *f, void *pv, size_t size,
+ const VMStateField *field,
+ JSONWriter *vmdesc)
+{
+ VirtIONet *n = pv;
+ VirtIODevice *vdev = VIRTIO_DEVICE(n);
+ struct vhost_dev *vhdev;
+ Error *local_error = NULL;
+ int ret;
+
+ vhdev = virtio_net_get_vhost(vdev);
+ if (vhdev == NULL) {
+ error_reportf_err(local_error,
+ "Error getting vhost back-end of %s device %s: ",
+ vdev->name, vdev->parent_obj.canonical_path);
+ return -1;
+ }
+
+ ret = vhost_save_backend_state(vhdev, f, &local_error);
+ if (ret < 0) {
+ error_reportf_err(local_error,
+ "Error saving back-end state of %s device %s: ",
+ vdev->name, vdev->parent_obj.canonical_path);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int vhost_user_net_load_state(QEMUFile *f, void *pv, size_t size,
+ const VMStateField *field)
+{
+ VirtIONet *n = pv;
+ VirtIODevice *vdev = VIRTIO_DEVICE(n);
+ struct vhost_dev *vhdev;
+ Error *local_error = NULL;
+ int ret;
+
+ vhdev = virtio_net_get_vhost(vdev);
+ if (vhdev == NULL) {
+ error_reportf_err(local_error,
+ "Error getting vhost back-end of %s device %s: ",
+ vdev->name, vdev->parent_obj.canonical_path);
+ return -1;
+ }
+
+ ret = vhost_load_backend_state(vhdev, f, &local_error);
+ if (ret < 0) {
+ error_reportf_err(local_error,
+ "Error loading back-end state of %s device %s: ",
+ vdev->name, vdev->parent_obj.canonical_path);
+ return ret;
+ }
+
+ return 0;
+}
+
+static bool vhost_user_net_is_internal_migration(void *opaque)
+{
+ VirtIONet *n = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(n);
+ struct vhost_dev *vhdev;
+
+ vhdev = virtio_net_get_vhost(vdev);
+ if (vhdev == NULL) {
+ return false;
+ }
+
+ return vhost_supports_device_state(vhdev);
+}
+
+static const VMStateDescription vhost_user_net_backend_state = {
+ .name = "virtio-net-device/backend",
+ .version_id = 0,
+ .needed = vhost_user_net_is_internal_migration,
+ .fields = (const VMStateField[]) {
+ {
+ .name = "backend",
+ .info = &(const VMStateInfo) {
+ .name = "virtio-net vhost-user backend state",
+ .get = vhost_user_net_load_state,
+ .put = vhost_user_net_save_state,
+ },
+ },
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_virtio_net_device = {
.name = "virtio-net-device",
.version_id = VIRTIO_NET_VM_VERSION,
@@ -3389,6 +3500,7 @@ static const VMStateDescription vmstate_virtio_net_device = {
},
.subsections = (const VMStateDescription * const []) {
&vmstate_virtio_net_rss,
+ &vhost_user_net_backend_state,
NULL
}
};
@@ -3950,29 +4062,6 @@ static bool dev_unplug_pending(void *opaque)
return vdc->primary_unplug_pending(dev);
}
-static struct vhost_dev *virtio_net_get_vhost(VirtIODevice *vdev)
-{
- VirtIONet *n = VIRTIO_NET(vdev);
- NetClientState *nc;
- struct vhost_net *net;
-
- if (!n->nic) {
- return NULL;
- }
-
- nc = qemu_get_queue(n->nic);
- if (!nc) {
- return NULL;
- }
-
- net = get_vhost_net(nc->peer);
- if (!net) {
- return NULL;
- }
-
- return &net->dev;
-}
-
static const VMStateDescription vmstate_virtio_net = {
.name = "virtio-net",
.minimum_version_id = VIRTIO_NET_VM_VERSION,
--
MST
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [PULL 00/48] virtio,pc,pci: features, fixes, cleanups
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (47 preceding siblings ...)
2025-01-15 18:11 ` [PULL 48/48] virtio-net: vhost-user: Implement internal migration Michael S. Tsirkin
@ 2025-01-15 18:15 ` David Woodhouse
2025-01-15 22:42 ` Michael S. Tsirkin
2025-01-16 7:06 ` Michael S. Tsirkin
2025-01-16 22:10 ` Stefan Hajnoczi
50 siblings, 1 reply; 56+ messages in thread
From: David Woodhouse @ 2025-01-15 18:15 UTC (permalink / raw)
To: Michael S. Tsirkin, qemu-devel; +Cc: Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 1115 bytes --]
On Wed, 2025-01-15 at 13:08 -0500, Michael S. Tsirkin wrote:
> The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
>
> Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging (2025-01-14 12:46:56 -0500)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
>
> for you to fetch changes up to 60f543ad917fad731e39ff8ce2ca83b9a9cc9d90:
>
> virtio-net: vhost-user: Implement internal migration (2025-01-15 13:07:34 -0500)
>
> ----------------------------------------------------------------
> virtio,pc,pci: features, fixes, cleanups
>
> The big thing here are:
> stage-1 translation in vtd
> internal migration in vhost-user
> ghes driver preparation for error injection
> new resource uuid feature in virtio gpu
>
> And as usual, fixes and cleanups.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Should I be concerned that the vmclock device isn't in this PR?
https://lore.kernel.org/qemu-devel/20250109080033-mutt-send-email-mst@kernel.org/
[-- Attachment #2: smime.p7s --]
[-- Type: application/pkcs7-signature, Size: 5069 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PULL 00/48] virtio,pc,pci: features, fixes, cleanups
2025-01-15 18:15 ` [PULL 00/48] virtio,pc,pci: features, fixes, cleanups David Woodhouse
@ 2025-01-15 22:42 ` Michael S. Tsirkin
2025-01-15 23:05 ` David Woodhouse
0 siblings, 1 reply; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-15 22:42 UTC (permalink / raw)
To: David Woodhouse; +Cc: qemu-devel, Peter Maydell
On Wed, Jan 15, 2025 at 07:15:18PM +0100, David Woodhouse wrote:
> On Wed, 2025-01-15 at 13:08 -0500, Michael S. Tsirkin wrote:
> > The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
> >
> > Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging (2025-01-14 12:46:56 -0500)
> >
> > are available in the Git repository at:
> >
> > https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
> >
> > for you to fetch changes up to 60f543ad917fad731e39ff8ce2ca83b9a9cc9d90:
> >
> > virtio-net: vhost-user: Implement internal migration (2025-01-15 13:07:34 -0500)
> >
> > ----------------------------------------------------------------
> > virtio,pc,pci: features, fixes, cleanups
> >
> > The big thing here are:
> > stage-1 translation in vtd
> > internal migration in vhost-user
> > ghes driver preparation for error injection
> > new resource uuid feature in virtio gpu
> >
> > And as usual, fixes and cleanups.
> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>
> Should I be concerned that the vmclock device isn't in this PR?
>
> https://lore.kernel.org/qemu-devel/20250109080033-mutt-send-email-mst@kernel.org/
>
Oops.. it was there :( Dropped by mistake in a rebase.
I'll redo the pull, thanks!
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PULL 00/48] virtio,pc,pci: features, fixes, cleanups
2025-01-15 22:42 ` Michael S. Tsirkin
@ 2025-01-15 23:05 ` David Woodhouse
2025-01-16 7:05 ` Michael S. Tsirkin
0 siblings, 1 reply; 56+ messages in thread
From: David Woodhouse @ 2025-01-15 23:05 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Peter Maydell
On 15 January 2025 23:42:41 CET, "Michael S. Tsirkin" <mst@redhat.com> wrote:
>On Wed, Jan 15, 2025 at 07:15:18PM +0100, David Woodhouse wrote:
>> On Wed, 2025-01-15 at 13:08 -0500, Michael S. Tsirkin wrote:
>> > The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
>> >
>> > Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging (2025-01-14 12:46:56 -0500)
>> >
>> > are available in the Git repository at:
>> >
>> > https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
>> >
>> > for you to fetch changes up to 60f543ad917fad731e39ff8ce2ca83b9a9cc9d90:
>> >
>> > virtio-net: vhost-user: Implement internal migration (2025-01-15 13:07:34 -0500)
>> >
>> > ----------------------------------------------------------------
>> > virtio,pc,pci: features, fixes, cleanups
>> >
>> > The big thing here are:
>> > stage-1 translation in vtd
>> > internal migration in vhost-user
>> > ghes driver preparation for error injection
>> > new resource uuid feature in virtio gpu
>> >
>> > And as usual, fixes and cleanups.
>> >
>> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>>
>> Should I be concerned that the vmclock device isn't in this PR?
>>
>> https://lore.kernel.org/qemu-devel/20250109080033-mutt-send-email-mst@kernel.org/
>>
>
>Oops.. it was there :( Dropped by mistake in a rebase.
>I'll redo the pull, thanks!
>
If it's easier, I could just round it up with the pull request I need to send tomorro^W later today anyway?
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PULL 00/48] virtio,pc,pci: features, fixes, cleanups
2025-01-15 23:05 ` David Woodhouse
@ 2025-01-16 7:05 ` Michael S. Tsirkin
2025-01-16 14:06 ` David Woodhouse
0 siblings, 1 reply; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-16 7:05 UTC (permalink / raw)
To: David Woodhouse; +Cc: qemu-devel, Peter Maydell
On Thu, Jan 16, 2025 at 12:05:59AM +0100, David Woodhouse wrote:
> On 15 January 2025 23:42:41 CET, "Michael S. Tsirkin" <mst@redhat.com> wrote:
> >On Wed, Jan 15, 2025 at 07:15:18PM +0100, David Woodhouse wrote:
> >> On Wed, 2025-01-15 at 13:08 -0500, Michael S. Tsirkin wrote:
> >> > The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
> >> >
> >> > Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging (2025-01-14 12:46:56 -0500)
> >> >
> >> > are available in the Git repository at:
> >> >
> >> > https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
> >> >
> >> > for you to fetch changes up to 60f543ad917fad731e39ff8ce2ca83b9a9cc9d90:
> >> >
> >> > virtio-net: vhost-user: Implement internal migration (2025-01-15 13:07:34 -0500)
> >> >
> >> > ----------------------------------------------------------------
> >> > virtio,pc,pci: features, fixes, cleanups
> >> >
> >> > The big thing here are:
> >> > stage-1 translation in vtd
> >> > internal migration in vhost-user
> >> > ghes driver preparation for error injection
> >> > new resource uuid feature in virtio gpu
> >> >
> >> > And as usual, fixes and cleanups.
> >> >
> >> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> >>
> >> Should I be concerned that the vmclock device isn't in this PR?
> >>
> >> https://lore.kernel.org/qemu-devel/20250109080033-mutt-send-email-mst@kernel.org/
> >>
> >
> >Oops.. it was there :( Dropped by mistake in a rebase.
> >I'll redo the pull, thanks!
> >
>
> If it's easier, I could just round it up with the pull request I need to send tomorro^W later today anyway?
Yes pls do. You can add:
Acked-by: Michael S. Tsirkin <mst@redhat.com>
but, I noticed checkpatch warnings:
3634039b93cc51816263e0cb5ba32e1b61142d5d:89: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
3634039b93cc51816263e0cb5ba32e1b61142d5d:366: WARNING: added, moved or deleted file(s) imported from Linux, are you using scripts/update-linux-headers.sh?
3634039b93cc51816263e0cb5ba32e1b61142d5d:366: ERROR: headers imported from Linux should be self-contained in a patch with no other changes
Please address.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PULL 00/48] virtio,pc,pci: features, fixes, cleanups
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (48 preceding siblings ...)
2025-01-15 18:15 ` [PULL 00/48] virtio,pc,pci: features, fixes, cleanups David Woodhouse
@ 2025-01-16 7:06 ` Michael S. Tsirkin
2025-01-16 22:10 ` Stefan Hajnoczi
50 siblings, 0 replies; 56+ messages in thread
From: Michael S. Tsirkin @ 2025-01-16 7:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
On Wed, Jan 15, 2025 at 01:08:28PM -0500, Michael S. Tsirkin wrote:
> The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
>
> Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging (2025-01-14 12:46:56 -0500)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
>
> for you to fetch changes up to 60f543ad917fad731e39ff8ce2ca83b9a9cc9d90:
>
> virtio-net: vhost-user: Implement internal migration (2025-01-15 13:07:34 -0500)
OK I missed including David's patch but he'll merge it himself.
So the request stands.
> ----------------------------------------------------------------
> virtio,pc,pci: features, fixes, cleanups
>
> The big thing here are:
> stage-1 translation in vtd
> internal migration in vhost-user
> ghes driver preparation for error injection
> new resource uuid feature in virtio gpu
>
> And as usual, fixes and cleanups.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>
> ----------------------------------------------------------------
> Clément Mathieu--Drif (4):
> intel_iommu: Check if the input address is canonical
> intel_iommu: Set accessed and dirty bits during stage-1 translation
> intel_iommu: Add an internal API to find an address space with PASID
> intel_iommu: Add support for PASID-based device IOTLB invalidation
>
> Dorinda Bassey (1):
> virtio-gpu: Add definition for resource_uuid feature
>
> Igor Mammedov (6):
> tests: acpi: whitelist expected blobs
> cpuhp: make sure that remove events are handled within the same SCI
> tests: acpi: update expected blobs
> tests: acpi: whitelist expected blobs
> pci: acpi: Windows 'PCI Label Id' bug workaround
> tests: acpi: update expected blobs
>
> Laurent Vivier (2):
> vhost: Add stubs for the migration state transfer interface
> virtio-net: vhost-user: Implement internal migration
>
> Li Zhijian (1):
> hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`
>
> Mauro Carvalho Chehab (16):
> acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED
> acpi/ghes: simplify acpi_ghes_record_errors() code
> acpi/ghes: simplify the per-arch caller to build HEST table
> acpi/ghes: better handle source_id and notification
> acpi/ghes: Fix acpi_ghes_record_errors() argument
> acpi/ghes: Remove a duplicated out of bounds check
> acpi/ghes: Change the type for source_id
> acpi/ghes: don't check if physical_address is not zero
> acpi/ghes: make the GHES record generation more generic
> acpi/ghes: better name GHES memory error function
> acpi/ghes: don't crash QEMU if ghes GED is not found
> acpi/ghes: rename etc/hardware_error file macros
> acpi/ghes: better name the offset of the hardware error firmware
> acpi/ghes: move offset calculus to a separate function
> acpi/ghes: Change ghes fill logic to work with only one source
> docs: acpi_hest_ghes: fix documentation for CPER size
>
> Nicholas Piggin (1):
> pci/msix: Fix msix pba read vector poll end calculation
>
> Sebastian Ott (1):
> pci: ensure valid link status bits for downstream ports
>
> Yi Liu (2):
> intel_iommu: Rename slpte to pte
> intel_iommu: Implement stage-1 translation
>
> Yu Zhang (1):
> intel_iommu: Use the latest fault reasons defined by spec
>
> Zhenzhong Duan (13):
> intel_iommu: Make pasid entry type check accurate
> intel_iommu: Add a placeholder variable for scalable mode stage-1 translation
> intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation
> intel_iommu: Check stage-1 translation result with interrupt range
> intel_iommu: Flush stage-1 cache in iotlb invalidation
> intel_iommu: Process PASID-based iotlb invalidation
> intel_iommu: piotlb invalidation should notify unmap
> tests/acpi: q35: allow DMAR acpi table changes
> intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2
> tests/acpi: q35: Update host address width in DMAR
> intel_iommu: Introduce a property x-flts for stage-1 translation
> intel_iommu: Introduce a property to control FS1GP cap bit setting
> tests/qtest: Add intel-iommu test
>
> hw/i386/intel_iommu_internal.h | 101 ++-
> include/hw/acpi/ghes.h | 16 +-
> include/hw/i386/intel_iommu.h | 8 +-
> include/hw/virtio/vhost.h | 23 +
> include/hw/virtio/virtio-gpu.h | 3 +
> hw/acpi/cpu.c | 43 +-
> hw/acpi/generic_event_device.c | 4 +-
> hw/acpi/ghes-stub.c | 2 +-
> hw/acpi/ghes.c | 256 ++++----
> hw/arm/virt-acpi-build.c | 5 +-
> hw/display/vhost-user-gpu.c | 8 +
> hw/display/virtio-gpu-base.c | 3 +
> hw/i386/acpi-build.c | 33 +-
> hw/i386/intel_iommu.c | 734 +++++++++++++++++-----
> hw/i386/pc.c | 1 +
> hw/mem/cxl_type3.c | 2 +-
> hw/net/virtio-net.c | 135 +++-
> hw/pci/msix.c | 2 +-
> hw/pci/pcie.c | 12 +-
> target/arm/kvm.c | 2 +-
> tests/qtest/intel-iommu-test.c | 64 ++
> MAINTAINERS | 1 +
> docs/specs/acpi_hest_ghes.rst | 6 +-
> tests/data/acpi/x86/pc/DSDT | Bin 8526 -> 8611 bytes
> tests/data/acpi/x86/pc/DSDT.acpierst | Bin 8437 -> 8522 bytes
> tests/data/acpi/x86/pc/DSDT.acpihmat | Bin 9851 -> 9936 bytes
> tests/data/acpi/x86/pc/DSDT.bridge | Bin 15397 -> 15482 bytes
> tests/data/acpi/x86/pc/DSDT.cphp | Bin 8990 -> 9075 bytes
> tests/data/acpi/x86/pc/DSDT.dimmpxm | Bin 10180 -> 10265 bytes
> tests/data/acpi/x86/pc/DSDT.hpbridge | Bin 8477 -> 8562 bytes
> tests/data/acpi/x86/pc/DSDT.hpbrroot | Bin 5033 -> 5100 bytes
> tests/data/acpi/x86/pc/DSDT.ipmikcs | Bin 8598 -> 8683 bytes
> tests/data/acpi/x86/pc/DSDT.memhp | Bin 9885 -> 9970 bytes
> tests/data/acpi/x86/pc/DSDT.nohpet | Bin 8384 -> 8469 bytes
> tests/data/acpi/x86/pc/DSDT.numamem | Bin 8532 -> 8617 bytes
> tests/data/acpi/x86/pc/DSDT.roothp | Bin 12319 -> 12404 bytes
> tests/data/acpi/x86/q35/DMAR.dmar | Bin 120 -> 120 bytes
> tests/data/acpi/x86/q35/DSDT | Bin 8355 -> 8440 bytes
> tests/data/acpi/x86/q35/DSDT.acpierst | Bin 8372 -> 8457 bytes
> tests/data/acpi/x86/q35/DSDT.acpihmat | Bin 9680 -> 9765 bytes
> tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x | Bin 12565 -> 12650 bytes
> tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator | Bin 8634 -> 8719 bytes
> tests/data/acpi/x86/q35/DSDT.applesmc | Bin 8401 -> 8486 bytes
> tests/data/acpi/x86/q35/DSDT.bridge | Bin 11968 -> 12053 bytes
> tests/data/acpi/x86/q35/DSDT.core-count | Bin 12913 -> 12998 bytes
> tests/data/acpi/x86/q35/DSDT.core-count2 | Bin 33770 -> 33855 bytes
> tests/data/acpi/x86/q35/DSDT.cphp | Bin 8819 -> 8904 bytes
> tests/data/acpi/x86/q35/DSDT.cxl | Bin 13146 -> 13231 bytes
> tests/data/acpi/x86/q35/DSDT.dimmpxm | Bin 10009 -> 10094 bytes
> tests/data/acpi/x86/q35/DSDT.ipmibt | Bin 8430 -> 8515 bytes
> tests/data/acpi/x86/q35/DSDT.ipmismbus | Bin 8443 -> 8528 bytes
> tests/data/acpi/x86/q35/DSDT.ivrs | Bin 8372 -> 8457 bytes
> tests/data/acpi/x86/q35/DSDT.memhp | Bin 9714 -> 9799 bytes
> tests/data/acpi/x86/q35/DSDT.mmio64 | Bin 9485 -> 9570 bytes
> tests/data/acpi/x86/q35/DSDT.multi-bridge | Bin 13208 -> 13293 bytes
> tests/data/acpi/x86/q35/DSDT.noacpihp | Bin 8235 -> 8302 bytes
> tests/data/acpi/x86/q35/DSDT.nohpet | Bin 8213 -> 8298 bytes
> tests/data/acpi/x86/q35/DSDT.numamem | Bin 8361 -> 8446 bytes
> tests/data/acpi/x86/q35/DSDT.pvpanic-isa | Bin 8456 -> 8541 bytes
> tests/data/acpi/x86/q35/DSDT.thread-count | Bin 12913 -> 12998 bytes
> tests/data/acpi/x86/q35/DSDT.thread-count2 | Bin 33770 -> 33855 bytes
> tests/data/acpi/x86/q35/DSDT.tis.tpm12 | Bin 8961 -> 9046 bytes
> tests/data/acpi/x86/q35/DSDT.tis.tpm2 | Bin 8987 -> 9072 bytes
> tests/data/acpi/x86/q35/DSDT.type4-count | Bin 18589 -> 18674 bytes
> tests/data/acpi/x86/q35/DSDT.viot | Bin 14612 -> 14697 bytes
> tests/data/acpi/x86/q35/DSDT.xapic | Bin 35718 -> 35803 bytes
> tests/qtest/meson.build | 1 +
> 67 files changed, 1132 insertions(+), 333 deletions(-)
> create mode 100644 tests/qtest/intel-iommu-test.c
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PULL 00/48] virtio,pc,pci: features, fixes, cleanups
2025-01-16 7:05 ` Michael S. Tsirkin
@ 2025-01-16 14:06 ` David Woodhouse
0 siblings, 0 replies; 56+ messages in thread
From: David Woodhouse @ 2025-01-16 14:06 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 1082 bytes --]
On Thu, 2025-01-16 at 02:05 -0500, Michael S. Tsirkin wrote:
>
> Yes pls do. You can add:
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
>
> but, I noticed checkpatch warnings:
>
> 3634039b93cc51816263e0cb5ba32e1b61142d5d:89: WARNING: added, moved or
> deleted file(s), does MAINTAINERS need updating?
> 3634039b93cc51816263e0cb5ba32e1b61142d5d:366: WARNING: added, moved
> or deleted file(s) imported from Linux, are you using scripts/update-
> linux-headers.sh?
> 3634039b93cc51816263e0cb5ba32e1b61142d5d:366: ERROR: headers imported
> from Linux should be self-contained in a patch with no other changes
>
>
> Please address.
I've split it out into three commits now, first adding to update-linux-
headers.sh, then importing the new header, then finally the actual
vmclock support.
That pushes me *slightly* over the edge of calling it a trivial change,
so I've posted it one last time for review. Assuming nobody screams and
I don't have to make further changes, I'm happy to post a PR tomorrow,
or let you do it, as you prefer.
Thanks.
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^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PULL 00/48] virtio,pc,pci: features, fixes, cleanups
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
` (49 preceding siblings ...)
2025-01-16 7:06 ` Michael S. Tsirkin
@ 2025-01-16 22:10 ` Stefan Hajnoczi
50 siblings, 0 replies; 56+ messages in thread
From: Stefan Hajnoczi @ 2025-01-16 22:10 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.
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^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2025-01-16 22:11 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 02/48] pci: ensure valid link status bits for downstream ports Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 03/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 05/48] tests: acpi: update expected blobs Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 07/48] intel_iommu: Make pasid entry type check accurate Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 10/48] intel_iommu: Rename slpte to pte Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 11/48] intel_iommu: Implement stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 12/48] intel_iommu: Check if the input address is canonical Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 16/48] intel_iommu: Process PASID-based " Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 21/48] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 22/48] tests/acpi: q35: Update host address width in DMAR Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 25/48] tests/qtest: Add intel-iommu test Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 28/48] acpi/ghes: simplify acpi_ghes_record_errors() code Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 30/48] acpi/ghes: better handle source_id and notification Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 33/48] acpi/ghes: Change the type for source_id Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 34/48] acpi/ghes: don't check if physical_address is not zero Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 35/48] acpi/ghes: make the GHES record generation more generic Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 36/48] acpi/ghes: better name GHES memory error function Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 37/48] acpi/ghes: don't crash QEMU if ghes GED is not found Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 38/48] acpi/ghes: rename etc/hardware_error file macros Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 39/48] acpi/ghes: better name the offset of the hardware error firmware Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 40/48] acpi/ghes: move offset calculus to a separate function Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 41/48] acpi/ghes: Change ghes fill logic to work with only one source Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 42/48] docs: acpi_hest_ghes: fix documentation for CPER size Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 43/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 44/48] pci: acpi: Windows 'PCI Label Id' bug workaround Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 45/48] tests: acpi: update expected blobs Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 46/48] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 47/48] vhost: Add stubs for the migration state transfer interface Michael S. Tsirkin
2025-01-15 18:11 ` [PULL 48/48] virtio-net: vhost-user: Implement internal migration Michael S. Tsirkin
2025-01-15 18:15 ` [PULL 00/48] virtio,pc,pci: features, fixes, cleanups David Woodhouse
2025-01-15 22:42 ` Michael S. Tsirkin
2025-01-15 23:05 ` David Woodhouse
2025-01-16 7:05 ` Michael S. Tsirkin
2025-01-16 14:06 ` David Woodhouse
2025-01-16 7:06 ` Michael S. Tsirkin
2025-01-16 22:10 ` Stefan Hajnoczi
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