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[83.11.188.80]) by smtp.gmail.com with ESMTPSA id b10-20020a170906490a00b009a1fef32ce6sm6392461ejq.177.2023.08.29.13.05.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Aug 2023 13:05:49 -0700 (PDT) Message-ID: Date: Tue, 29 Aug 2023 22:05:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: PCIe: SLT attribute mismatch: 0xFF020100 instead of 0x20100 Content-Language: pl-PL, en-GB, en-HK To: "Michael S. Tsirkin" , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Cc: Peter Maydell , qemu-devel@nongnu.org, Gowtham Siddarth , Marcel Apfelbaum References: <56aa4acb-d54c-a457-5a32-9258cec1ac96@linaro.org> <20230829093909-mutt-send-email-mst@kernel.org> <43653986-c04f-0076-637b-9061f9702f77@linaro.org> <20230829130617-mutt-send-email-mst@kernel.org> From: Marcin Juszkiewicz Organization: Linaro In-Reply-To: <20230829130617-mutt-send-email-mst@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=marcin.juszkiewicz@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org W dniu 29.08.2023 o 19:07, Michael S. Tsirkin pisze: > No - it depends on secondart bus type and only applies to bridges. > Also we need compat machinery. > Marcin could you pls test the following? Works fine: 822 : Check Type 1 config header rules : Result: PASS > > diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h > index ea54a81a15..5cd452115a 100644 > --- a/include/hw/pci/pci_bridge.h > +++ b/include/hw/pci/pci_bridge.h > @@ -77,6 +77,9 @@ struct PCIBridge { > > pci_map_irq_fn map_irq; > const char *bus_name; > + > + /* SLT is RO for PCIE to PCIE bridges, but old QEMU versions had it RW */ > + bool pcie_writeable_slt_bug; > }; > > #define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr" > diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c > index e7b9345615..6a4e38856d 100644 > --- a/hw/pci/pci_bridge.c > +++ b/hw/pci/pci_bridge.c > @@ -38,6 +38,7 @@ > #include "qapi/error.h" > #include "hw/acpi/acpi_aml_interface.h" > #include "hw/acpi/pci.h" > +#include "hw/qdev-properties.h" > > /* PCI bridge subsystem vendor ID helper functions */ > #define PCI_SSVID_SIZEOF 8 > @@ -385,6 +386,11 @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename) > pci_bridge_region_init(br); > QLIST_INIT(&sec_bus->child); > QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); > + > + /* For express secondary buses, secondary latency timer is RO 0 */ > + if (pci_bus_is_express(sec_bus) && !br->pcie_writeable_slt_bug) { > + dev->wmask[PCI_SEC_LATENCY_TIMER] = 0; > + } > } > > /* default qdev clean up function for PCI-to-PCI bridge */ > @@ -466,10 +472,18 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, > return 0; > } > > +static Property pci_bridge_properties[] = { > + DEFINE_PROP_BOOL("x-pci-express-writeable-slt-bug", PCIBridge, > + pcie_writeable_slt_bug, false), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > static void pci_bridge_class_init(ObjectClass *klass, void *data) > { > AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); > + DeviceClass *k = DEVICE_CLASS(klass); > > + device_class_set_props(k, pci_bridge_properties); > adevc->build_dev_aml = build_pci_bridge_aml; > } > > >