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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e47b7d12sm14366111f8f.58.2025.03.03.02.52.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Mar 2025 02:52:20 -0800 (PST) Message-ID: Date: Mon, 3 Mar 2025 11:52:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 036/162] tcg: Convert muluh to TCGOutOpBinary To: Richard Henderson , qemu-devel@nongnu.org References: <20250216231012.2808572-1-richard.henderson@linaro.org> <20250216231012.2808572-37-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250216231012.2808572-37-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 17/2/25 00:08, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/aarch64/tcg-target-has.h | 2 -- > tcg/arm/tcg-target-has.h | 1 - > tcg/i386/tcg-target-has.h | 2 -- > tcg/loongarch64/tcg-target-has.h | 2 -- > tcg/mips/tcg-target-has.h | 2 -- > tcg/ppc/tcg-target-has.h | 2 -- > tcg/riscv/tcg-target-has.h | 2 -- > tcg/s390x/tcg-target-has.h | 2 -- > tcg/sparc64/tcg-target-has.h | 2 -- > tcg/tcg-has.h | 1 - > tcg/tci/tcg-target-has.h | 2 -- > tcg/tcg-op.c | 7 +++--- > tcg/tcg.c | 16 ++++++-------- > tcg/aarch64/tcg-target.c.inc | 21 ++++++++++++++---- > tcg/arm/tcg-target.c.inc | 4 ++++ > tcg/i386/tcg-target.c.inc | 4 ++++ > tcg/loongarch64/tcg-target.c.inc | 24 +++++++++++++-------- > tcg/mips/tcg-target.c.inc | 37 ++++++++++++++++++-------------- > tcg/ppc/tcg-target.c.inc | 20 ++++++++++------- > tcg/riscv/tcg-target.c.inc | 24 +++++++++++++++------ > tcg/s390x/tcg-target.c.inc | 4 ++++ > tcg/sparc64/tcg-target.c.inc | 23 +++++++++++++++----- > tcg/tci/tcg-target.c.inc | 4 ++++ > 23 files changed, 126 insertions(+), 82 deletions(-) > diff --git a/tcg/tcg.c b/tcg/tcg.c > index ec64a235d0..2741048353 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -1022,6 +1022,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = { > OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), > OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv), > OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul), > + OUTOP(INDEX_op_muluh_i32, TCGOutOpBinary, outop_muluh), > + OUTOP(INDEX_op_muluh_i64, TCGOutOpBinary, outop_muluh), > OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand), > OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg), > OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor), > @@ -2280,8 +2282,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) > return TCG_TARGET_HAS_mulu2_i32; > case INDEX_op_muls2_i32: > return TCG_TARGET_HAS_muls2_i32; > - case INDEX_op_muluh_i32: > - return TCG_TARGET_HAS_muluh_i32; > case INDEX_op_mulsh_i32: > return TCG_TARGET_HAS_mulsh_i32; > case INDEX_op_bswap16_i32: > @@ -2362,8 +2362,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) > return TCG_TARGET_HAS_mulu2_i64; > case INDEX_op_muls2_i64: > return TCG_TARGET_HAS_muls2_i64; > - case INDEX_op_muluh_i64: > - return TCG_TARGET_HAS_muluh_i64; > case INDEX_op_mulsh_i64: > return TCG_TARGET_HAS_mulsh_i64; > > @@ -3876,7 +3874,6 @@ liveness_pass_1(TCGContext *s) > QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, link, op_prev) { > int nb_iargs, nb_oargs; > TCGOpcode opc_new, opc_new2; > - bool have_opc_new2; > TCGLifeData arg_life = 0; > TCGTemp *ts; > TCGOpcode opc = op->opc; > @@ -4036,22 +4033,18 @@ liveness_pass_1(TCGContext *s) > case INDEX_op_mulu2_i32: > opc_new = INDEX_op_mul; > opc_new2 = INDEX_op_muluh_i32; > - have_opc_new2 = TCG_TARGET_HAS_muluh_i32; Maybe cleaner to use 'have_opc_new2 = true', checking for have_opc_new2 && tcg_op_supported(), then remove have_opc_new2 in 2 commits in "Convert mulsh to TCGOutOpBinary"; otherwise maybe mention that this commit is tied to mulsh conversion? > goto do_mul2; > case INDEX_op_muls2_i32: > opc_new = INDEX_op_mul; > opc_new2 = INDEX_op_mulsh_i32; > - have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; > goto do_mul2; > case INDEX_op_mulu2_i64: > opc_new = INDEX_op_mul; > opc_new2 = INDEX_op_muluh_i64; > - have_opc_new2 = TCG_TARGET_HAS_muluh_i64; > goto do_mul2; > case INDEX_op_muls2_i64: > opc_new = INDEX_op_mul; > opc_new2 = INDEX_op_mulsh_i64; > - have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; > goto do_mul2; > do_mul2: > nb_iargs = 2; > @@ -4065,7 +4058,8 @@ liveness_pass_1(TCGContext *s) > op->opc = opc = opc_new; > op->args[1] = op->args[2]; > op->args[2] = op->args[3]; > - } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { > + } else if (arg_temp(op->args[0])->state == TS_DEAD && > + tcg_op_supported(opc_new2, TCGOP_TYPE(op), 0)) { > /* The low part of the operation is dead; generate the high. */ > op->opc = opc = opc_new2; > op->args[0] = op->args[1]; > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index 95c2645226..ad62d877c7 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -1743,6 +1743,27 @@ static const TCGOutOpBinary outop_mul = { > .out_rrr = tgen_mul, > }; > > +static void tgen_muluh(TCGContext *s, TCGType type, > + TCGReg a0, TCGReg a1, TCGReg a2) > +{ > + if (use_mips32r6_instructions) { Similarly for style: insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; > + if (type == TCG_TYPE_I32) { > + tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); > + } else { > + tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); > + } > + } else { > + MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; > + tcg_out_opc_reg(s, insn, 0, a1, a2); > + tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); > + } > +} > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index ff685037d7..65246cc450 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -2021,6 +2021,23 @@ static const TCGOutOpBinary outop_mul = { > .out_rrr = tgen_mul, > }; > > +static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags) > +{ > + return type == TCG_TYPE_I32 ? C_NotImplemented : C_O1_I2(r, r, r); > +} > + > @@ -2379,11 +2396,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); > break; > > - case INDEX_op_muluh_i32: > - case INDEX_op_muluh_i64: > - tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); > - break; > - > case INDEX_op_mb: > tcg_out_mb(s, a0); > break; Please mention we remove the unreachable mulsh_i32 leftover from commit aeb6326ec5e ("tcg/riscv: Require TCG_TARGET_REG_BITS == 64"). Reviewed-by: Philippe Mathieu-Daudé