From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 2/7] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode
Date: Sun, 3 Dec 2017 07:03:46 -0800 [thread overview]
Message-ID: <ff7a4f36-1892-4e1b-3ab3-7282fb8cbdf7@linaro.org> (raw)
In-Reply-To: <1512153879-5291-3-git-send-email-peter.maydell@linaro.org>
On 12/01/2017 10:44 AM, Peter Maydell wrote:
> In ARMv7M the CPU ignores explicit writes to CONTROL.SPSEL
> in Handler mode. In v8M the behaviour is slightly different:
> writes to the bit are permitted but will have no effect.
>
> We've already done the hard work to handle the value in
> CONTROL.SPSEL being out of sync with what stack pointer is
> actually in use, so all we need to do to fix this last loose
> end is to update the condition we use to guard whether we
> call write_v7m_control_spsel() on the register write.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/helper.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2017-12-03 15:03 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-01 18:44 [Qemu-devel] [PATCH 0/7] armv8m: Implement TT, and other bugfixes Peter Maydell
2017-12-01 18:44 ` [Qemu-devel] [PATCH 1/7] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads Peter Maydell
2017-12-03 14:58 ` Richard Henderson
2017-12-05 18:54 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 2/7] target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode Peter Maydell
2017-12-03 15:03 ` Richard Henderson [this message]
2017-12-01 18:44 ` [Qemu-devel] [PATCH 3/7] target/arm: Add missing M profile case to regime_is_user() Peter Maydell
2017-12-03 15:04 ` Richard Henderson
2017-12-05 18:58 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 4/7] target/arm: Split M profile MNegPri mmu index into user and priv Peter Maydell
2017-12-03 15:09 ` Richard Henderson
2017-12-05 21:23 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-12-07 11:07 ` Peter Maydell
2017-12-07 14:15 ` Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 5/7] target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv() Peter Maydell
2017-12-03 15:12 ` Richard Henderson
2017-12-05 21:24 ` Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 6/7] target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8() Peter Maydell
2017-12-03 15:16 ` Richard Henderson
2017-12-05 21:27 ` Philippe Mathieu-Daudé
2017-12-01 18:44 ` [Qemu-devel] [PATCH 7/7] target/arm: Implement TT instruction Peter Maydell
2017-12-03 16:04 ` Richard Henderson
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