From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [PATCH v2 03/27] target/riscv: Add the virtulisation mode
Date: Fri, 25 Oct 2019 16:23:18 -0700 [thread overview]
Message-ID: <ff8c971109f1159e2fff7a64ea0b58533c329302.1572045716.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1572045716.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 91e1c56fc4..469dcbd1c0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -117,6 +117,8 @@ struct CPURISCVState {
#ifndef CONFIG_USER_ONLY
target_ulong priv;
+ /* This contains QEMU specific information about the virt state. */
+ target_ulong virt;
target_ulong resetvec;
target_ulong mhartid;
@@ -248,6 +250,8 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_virt_enabled(CPURISCVState *env);
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index e99834856c..b4119cc002 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -422,6 +422,9 @@
#define PRV_H 2 /* Reserved */
#define PRV_M 3
+/* Virtulisation Register Fields */
+#define VIRT_ONOFF 1
+
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7fc00000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 31f553efb9..0306f3181d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -82,6 +82,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+bool riscv_cpu_virt_enabled(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ return get_field(env->virt, VIRT_ONOFF);
+}
+
+void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.23.0
next prev parent reply other threads:[~2019-10-25 23:36 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 23:23 [PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-10-25 23:23 ` [PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-10-25 23:23 ` [PATCH v2 02/27] target/riscv: Add the Hypervisor extension Alistair Francis
2019-10-25 23:23 ` Alistair Francis [this message]
2019-10-25 23:23 ` [PATCH v2 04/27] target/riscv: Add the force HS exception mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-10-25 23:23 ` [PATCH v2 07/27] target/riscv: Print priv and virt in disas log Alistair Francis
2019-10-25 23:23 ` [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-10-25 23:23 ` [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-10-25 23:23 ` [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-10-25 23:23 ` [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-10-25 23:23 ` [PATCH v2 12/27] target/riscv: Add virtual register swapping function Alistair Francis
2019-10-25 23:23 ` [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-10-25 23:23 ` [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-10-25 23:24 ` [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-10-25 23:24 ` [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-10-25 23:24 ` [PATCH v2 17/27] target/riscv: Add hypvervisor trap support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 19/27] target/riscv: Add hfence instructions Alistair Francis
2019-10-25 23:24 ` [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-10-25 23:24 ` [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-10-25 23:24 ` [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-10-25 23:24 ` [PATCH v2 23/27] target/riscv: Allow specifying MMU stage Alistair Francis
2019-10-25 23:24 ` [PATCH v2 24/27] target/riscv: Implement second stage MMU Alistair Francis
2019-10-25 23:24 ` [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-10-25 23:24 ` [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-10-25 23:24 ` [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
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