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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id r13-20020a05600c35cd00b003ede03e4369sm4643913wmq.33.2023.04.13.00.12.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Apr 2023 00:12:53 -0700 (PDT) Message-ID: Date: Thu, 13 Apr 2023 09:12:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v2 27/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org References: <20230411010512.5375-1-richard.henderson@linaro.org> <20230411010512.5375-28-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.083, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/12/23 22:18, Daniel Henrique Barboza wrote: > > > On 4/10/23 22:04, Richard Henderson wrote: >> The port currently does not support "oversize" guests, which >> means riscv32 can only target 32-bit guests.  We will soon be >> building TCG once for all guests.  This implies that we can >> only support riscv64. >> >> Since all Linux distributions target riscv64 not riscv32, >> this is not much of a restriction and simplifies the code. > > Code looks good but I got confused about the riscv32 implications you cited. > > Does this means that if someone happens to have a risc-v 32 bit host, with a > special Linux sauce that runs on that 32 bit risc-v host, this person won't be > able to build the riscv32 TCG target in that machine? Correct. At present, one is able to configure with such a host, and if one uses --target-list=x,y,z such that all of x, y or z are 32-bit guests the build should even succeed, and the result should probably work. However, if one does not use --target-list in configure, the build will #error out here: >> @@ -942,9 +913,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = { >>   #endif >>   }; >> -/* We don't support oversize guests */ >> -QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); >> - I am working on a patch set, not yet posted, which builds tcg/*.o twice, once for system mode and once for user-only. At which point riscv32 cannot build at all. I brought this patch forward from there in order to reduce churn. r~