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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c1b59f6sm2277356f8f.69.2025.01.30.07.13.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Jan 2025 07:13:31 -0800 (PST) Message-ID: Date: Thu, 30 Jan 2025 16:13:30 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 13/17] aspeed/soc: Add AST2700 support To: Jamin Lin , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , Alistair Francis , Cleber Rosa , Wainer dos Santos Moschetta , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" , Jinjie Ruan Cc: troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com References: <20240604054438.3424349-1-jamin_lin@aspeedtech.com> <20240604054438.3424349-14-jamin_lin@aspeedtech.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240604054438.3424349-14-jamin_lin@aspeedtech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Jamin, On 4/6/24 07:44, Jamin Lin wrote: > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU). > > AST2700 SOC and its interrupt controller are too complex to handle > in the common Aspeed SoC framework. We introduce a new ast2700 > class with instance_init and realize handlers. > > AST2700 is a 64 bits quad core cpus and support 8 watchdog. > Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8. > In addition, update AspeedSocState to support scuio, sli, sliio and intc. > > Add TYPE_ASPEED27X0_SOC machine type. > > The SDMC controller is unlocked at SPL stage. > At present, only supports to emulate booting > start from u-boot stage. Set SDMC controller > unlocked by default. > > In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts. > It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136. > And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to > GICINT or-gates instead of GIC device. > > Signed-off-by: Troy Lee > Signed-off-by: Jamin Lin > --- > hw/arm/aspeed_ast27x0.c | 563 ++++++++++++++++++++++++++++++++++++ > hw/arm/meson.build | 1 + > include/hw/arm/aspeed_soc.h | 28 +- > 3 files changed, 590 insertions(+), 2 deletions(-) > create mode 100644 hw/arm/aspeed_ast27x0.c > +static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) > +{ > + Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); > + AspeedSoCState *s = ASPEED_SOC(dev); > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); > + SysBusDevice *gicbusdev; > + DeviceState *gicdev; > + QList *redist_region_count; > + int i; > + > + gicbusdev = SYS_BUS_DEVICE(&a->gic); > + gicdev = DEVICE(&a->gic); > + qdev_prop_set_uint32(gicdev, "revision", 3); > + qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); > + qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); > + > + redist_region_count = qlist_new(); > + qlist_append_int(redist_region_count, sc->num_cpus); > + qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); > + > + if (!sysbus_realize(gicbusdev, errp)) { > + return false; > + } > + sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); > + sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); > + > + for (i = 0; i < sc->num_cpus; i++) { > + DeviceState *cpudev = DEVICE(&a->cpu[i]); > + int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9, VIRTUAL_PMU_IRQ = 7; > + int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; > + > + const int timer_irq[] = { > + [GTIMER_PHYS] = 14, > + [GTIMER_VIRT] = 11, > + [GTIMER_HYP] = 10, > + [GTIMER_SEC] = 13, > + }; > + int j; > + > + for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { > + qdev_connect_gpio_out(cpudev, j, > + qdev_get_gpio_in(gicdev, ppibase + timer_irq[j])); > + } > + > + qemu_irq irq = qdev_get_gpio_in(gicdev, > + ppibase + ARCH_GIC_MAINT_IRQ); > + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", > + 0, irq); > + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, > + qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); > + > + sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); > + sysbus_connect_irq(gicbusdev, i + sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); > + sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); > + sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, > + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); Your patch was merged around the same time Jinjie added NMI support (see commit b36a32ead1 "target/arm: Add support for Non-maskable Interrupt"). Should we add them now? > + } > + > + return true; > +}