From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
Alistair.Francis@wdc.com, palmer@dabbelt.com,
chihmin.chao@sifive.com, jimw@sifive.com, bmeng.cn@gmail.com
Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com
Subject: Re: [PATCH 3/3] remove redundant check for fpu csr read and write interface
Date: Mon, 13 Jan 2020 16:24:08 -1000 [thread overview]
Message-ID: <fff313b8-766e-f7e9-4044-837261d38def@linaro.org> (raw)
In-Reply-To: <20200110081220.891-3-zhiwei_liu@c-sky.com>
On 1/9/20 10:12 PM, LIU Zhiwei wrote:
> The read or write interface must be called after the predicate fs return 0.
> And the predicate will check (!env->debugger && !riscv_cpu_fp_enabled(env)),
> S0 no need to check again.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 24 ------------------------
> 1 file changed, 24 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
prev parent reply other threads:[~2020-01-14 2:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-10 8:12 [PATCH 1/3] select gdb fpu xml by single or double float extension LIU Zhiwei
2020-01-10 8:12 ` [PATCH 2/3] RISC-V: use FIELD macro to define tb flags LIU Zhiwei
2020-01-14 2:22 ` Richard Henderson
2020-01-10 8:12 ` [PATCH 3/3] remove redundant check for fpu csr read and write interface LIU Zhiwei
2020-01-14 2:24 ` Richard Henderson [this message]
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