[Qemu-devel] Re: Re: SH4: Implement FD bit

[Vladimir Prus <vladimir@codesourcery.com>]

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Aurelien Jarno wrote:

> On Tue, Dec 09, 2008 at 07:36:19PM +0300, Vladimir Prus wrote:
>> Aurelien Jarno wrote:
>> 
>> >> 
>> >> SH4 manual say that if a floating point instruction is executed while
>> >> FD bit in the status register is 1, an exception should be raised. QEMU
>> >> presently does not do that, so the kernel does not initialize FP state
>> >> for any thread, nor does it save/restore FP state. The most apparent
>> >> consequence is that while recent gcc/libc expect double-precision mode
>> >> to be set by kernel, they run in single-precision mode, and all FP code
>> >> produces wrong values.
>> >> 
>> >> This patch fixes this. It also fixes a couple of places where PC was
>> >> not updated before handling an exception, although both those places
>> >> deal with invalid instruction and don't lead to any user-visible bugs.
>> >> 
>> >> - Volodya
>> > 
>> > Thanks, applied.
>> 
>> Thanks, but it looks like one bit of the patch somehow did not
>> make it into SVN. Specifically, this:
>> 
>> @@ -504,6 +523,13 @@ static void _decode_opc(DisasContext * ctx)
>>               }
>>         }
>>  
>> +    /* The 0xfffd instruction is underfined, so we don't want to
>> +       raise fpu disable exception on it.  */
>> +    if (((ctx->opcode & 0xf000) == 0xf000)
>> +       && (ctx->opcode != 0xfffd))
>> +      {
>> +       CHECK_FPU_ENABLED
>> +      }
>> 
>> Is present in my post, and is not present in:
>> 
>>         http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5937
>> 
>> Maybe some merge issue?
> 
> Yes I haven't seen that one hunk of the patch has been rejected, so I
> missed this part. I have just tried to merge it by hand, but it is not
> possible to apply it. It looks like the patch was not done against the
> current SVN.
> 
> Care to resend it against the current SVN?

Attached is the remaining bit of the patch, against fresh SVN.

Thanks,
Volodya



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commit ffcb0cc661325b87995ae62dcdefa448e0b7296a
Author: Vladimir Prus <vladimir@codesourcery.com>
Date:   Mon Dec 1 19:28:32 2008 +0300

    SH: Implement FD bit
    
    	* target-sh4/cpu.h (cpu_get_tb_cpu_state): Include SR's FD bit in
    	the flags.
    	* target-sh4/helper.h (raise_fpu_disable, raise_slot_fpu_disable):
    	New helpers.
    	* targets-sh4/op_helper.c (helper_raise_fpu_disable)
    	(helper_raise_slot_fpu_disable): New.
    	* target-sh4/translate.c (CHECK_NOT_DELAY_SLOT, CHECK_PRIVILEGED):
    	Set PC to the right value.
    	(CHECK_FPU_ENABLED): New.
    	(_decode_opc): Use CHECK_FPU_ENABLED for FP instructions.

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index d6cfb7c..23a5d34 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -481,6 +481,15 @@ static void _decode_opc(DisasContext * ctx)
 #if 0
     fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
 #endif
+
+    /* The 0xfffd instruction is underfined, so we don't want to
+       raise fpu disable exception on it.  */
+    if (((ctx->opcode & 0xf000) == 0xf000)
+	&& (ctx->opcode != 0xfffd))      
+      {
+	CHECK_FPU_ENABLED
+      }
+
     switch (ctx->opcode) {
     case 0x0019:		/* div0u */
 	tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));