From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LAO2z-0008V4-Ch for qemu-devel@nongnu.org; Wed, 10 Dec 2008 07:20:09 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LAO2w-0008Tw-RD for qemu-devel@nongnu.org; Wed, 10 Dec 2008 07:20:09 -0500 Received: from [199.232.76.173] (port=49490 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LAO2w-0008Tt-Oc for qemu-devel@nongnu.org; Wed, 10 Dec 2008 07:20:06 -0500 Received: from main.gmane.org ([80.91.229.2]:56117 helo=ciao.gmane.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LAO2v-0001lY-Th for qemu-devel@nongnu.org; Wed, 10 Dec 2008 07:20:06 -0500 Received: from root by ciao.gmane.org with local (Exim 4.43) id 1LAO2s-0003DF-N6 for qemu-devel@nongnu.org; Wed, 10 Dec 2008 12:20:02 +0000 Received: from lvk-gate.cmc.msu.ru ([212.192.248.233]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 10 Dec 2008 12:20:02 +0000 Received: from vladimir by lvk-gate.cmc.msu.ru with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 10 Dec 2008 12:20:02 +0000 From: Vladimir Prus Date: Wed, 10 Dec 2008 14:04:27 +0300 Message-ID: References: <200812012022.02276.vladimir@codesourcery.com> <20081207224734.GD3591@volta.aurel32.net> <20081210091526.GA19379@volta.aurel32.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart12957317.AT7C57oNXr" Content-Transfer-Encoding: 7Bit Sender: news Subject: [Qemu-devel] Re: Re: SH4: Implement FD bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --nextPart12957317.AT7C57oNXr Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8Bit Aurelien Jarno wrote: > On Tue, Dec 09, 2008 at 07:36:19PM +0300, Vladimir Prus wrote: >> Aurelien Jarno wrote: >> >> >> >> >> SH4 manual say that if a floating point instruction is executed while >> >> FD bit in the status register is 1, an exception should be raised. QEMU >> >> presently does not do that, so the kernel does not initialize FP state >> >> for any thread, nor does it save/restore FP state. The most apparent >> >> consequence is that while recent gcc/libc expect double-precision mode >> >> to be set by kernel, they run in single-precision mode, and all FP code >> >> produces wrong values. >> >> >> >> This patch fixes this. It also fixes a couple of places where PC was >> >> not updated before handling an exception, although both those places >> >> deal with invalid instruction and don't lead to any user-visible bugs. >> >> >> >> - Volodya >> > >> > Thanks, applied. >> >> Thanks, but it looks like one bit of the patch somehow did not >> make it into SVN. Specifically, this: >> >> @@ -504,6 +523,13 @@ static void _decode_opc(DisasContext * ctx) >> } >> } >> >> + /* The 0xfffd instruction is underfined, so we don't want to >> + raise fpu disable exception on it. */ >> + if (((ctx->opcode & 0xf000) == 0xf000) >> + && (ctx->opcode != 0xfffd)) >> + { >> + CHECK_FPU_ENABLED >> + } >> >> Is present in my post, and is not present in: >> >> http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5937 >> >> Maybe some merge issue? > > Yes I haven't seen that one hunk of the patch has been rejected, so I > missed this part. I have just tried to merge it by hand, but it is not > possible to apply it. It looks like the patch was not done against the > current SVN. > > Care to resend it against the current SVN? Attached is the remaining bit of the patch, against fresh SVN. Thanks, Volodya --nextPart12957317.AT7C57oNXr Content-Type: text/x-diff; name="fd_remaining.diff" Content-Transfer-Encoding: 8Bit Content-Disposition: attachment; filename="fd_remaining.diff" commit ffcb0cc661325b87995ae62dcdefa448e0b7296a Author: Vladimir Prus Date: Mon Dec 1 19:28:32 2008 +0300 SH: Implement FD bit * target-sh4/cpu.h (cpu_get_tb_cpu_state): Include SR's FD bit in the flags. * target-sh4/helper.h (raise_fpu_disable, raise_slot_fpu_disable): New helpers. * targets-sh4/op_helper.c (helper_raise_fpu_disable) (helper_raise_slot_fpu_disable): New. * target-sh4/translate.c (CHECK_NOT_DELAY_SLOT, CHECK_PRIVILEGED): Set PC to the right value. (CHECK_FPU_ENABLED): New. (_decode_opc): Use CHECK_FPU_ENABLED for FP instructions. diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d6cfb7c..23a5d34 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -481,6 +481,15 @@ static void _decode_opc(DisasContext * ctx) #if 0 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); #endif + + /* The 0xfffd instruction is underfined, so we don't want to + raise fpu disable exception on it. */ + if (((ctx->opcode & 0xf000) == 0xf000) + && (ctx->opcode != 0xfffd)) + { + CHECK_FPU_ENABLED + } + switch (ctx->opcode) { case 0x0019: /* div0u */ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); --nextPart12957317.AT7C57oNXr--