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From: Vladimir Prus <vladimir@codesourcery.com>
Date: Fri, 12 Dec 2008 08:48:33 +0300
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Subject: [Qemu-devel] Re: SH: Improve the interrupt controller
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To: qemu-devel@nongnu.org

Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 22:52 Thu 11 Dec     , Vladimir Prus wrote:
>> 
>> This patch improves the intc implementation in these ways:
>> 
>>    - On interrupt, the priority mask in SSR is updated,
>>      if OPM register tells it should be
>>    - We check interrupt priority and compare it with
>>      priority mask
>>    - Priorities for IRL interrupts (which are fixed), are
>>      assigned
>>    - The ICR register is supported, and LVLMODE bit, which
>>      controls if interrupt is automatically de-asserted,
>>      is implemented
>>    - A bug where handling of paired set mask / clear mask
>>      registers was done backward is fixed
>>    - A bug where enabling a group did not work was fixed.
> I'll be better to split this patch in two on for the bug fix and one
> for the improvements

FWIW, the most intrusive change is the bugfix for groups, so such
split won't make the patch more reviewable.

> IMHO your patch need some coding style cleanup also

Can you be more specific?

- Volodya