From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:58813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RkAIR-0003zd-Ch for qemu-devel@nongnu.org; Mon, 09 Jan 2012 03:09:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RkAIP-0001RP-9P for qemu-devel@nongnu.org; Mon, 09 Jan 2012 03:09:35 -0500 Received: from lo.gmane.org ([80.91.229.12]:57659) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RkAIO-0001R5-F6 for qemu-devel@nongnu.org; Mon, 09 Jan 2012 03:09:33 -0500 Received: from list by lo.gmane.org with local (Exim 4.69) (envelope-from ) id 1RkAIJ-0005a3-3k for qemu-devel@nongnu.org; Mon, 09 Jan 2012 09:09:27 +0100 Received: from 93-34-200-238.ip51.fastwebnet.it ([93.34.200.238]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Mon, 09 Jan 2012 09:09:26 +0100 Received: from pbonzini by 93-34-200-238.ip51.fastwebnet.it with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Mon, 09 Jan 2012 09:09:26 +0100 From: Paolo Bonzini Date: Mon, 09 Jan 2012 09:09:13 +0100 Message-ID: References: <1326054468-5361-1-git-send-email-hpoussin@reactos.org> <1326054468-5361-9-git-send-email-hpoussin@reactos.org> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit In-Reply-To: <1326054468-5361-9-git-send-email-hpoussin@reactos.org> Subject: Re: [Qemu-devel] [PATCH 08/10] fdc: add CCR (Configuration Control Register) write register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 01/08/2012 09:27 PM, Hervé Poussineau wrote: > > Signed-off-by: Hervé Poussineau > --- > hw/fdc.c | 21 +++++++++++++++++++++ > 1 files changed, 21 insertions(+), 0 deletions(-) > > diff --git a/hw/fdc.c b/hw/fdc.c > index ddfa91f..67cd14f 100644 > --- a/hw/fdc.c > +++ b/hw/fdc.c > @@ -227,6 +227,7 @@ static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); > static uint32_t fdctrl_read_data(FDCtrl *fdctrl); > static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); > static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); > +static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); > > enum { > FD_DIR_WRITE = 0, > @@ -251,6 +252,7 @@ enum { > FD_REG_DSR = 0x04, > FD_REG_FIFO = 0x05, > FD_REG_DIR = 0x07, > + FD_REG_CCR = 0x07, > }; > > enum { > @@ -495,6 +497,8 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) > case FD_REG_FIFO: > fdctrl_write_data(fdctrl, value); > break; > + case FD_REG_CCR: > + fdctrl_write_ccr(fdctrl, value); > default: > break; > } > @@ -885,6 +889,23 @@ static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) > fdctrl->dsr = value; > } > > +/* Configuration control register: 0x07 (write) */ > +static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) > +{ > + /* Reset mode */ > + if (!(fdctrl->dor& FD_DOR_nRESET)) { > + FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); > + return; > + } > + FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); > + > + /* Only the rate selection bits used in AT mode, and we > + * store those in the DSR. > + */ > + fdctrl->dsr = (fdctrl->dsr& ~FD_DSR_DRATEMASK) | > + (value& FD_DSR_DRATEMASK); > +} > + > static int fdctrl_media_changed(FDrive *drv) > { > int ret; This should go before patch 7, shouldn't it? Paolo