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Wed, 10 Mar 2021 05:59:45 -0500 (EST) Received: from localhost (disaster-area.hh.sledj.net [local]) by disaster-area.hh.sledj.net (OpenSMTPD) with ESMTPA id bdade7b0; Wed, 10 Mar 2021 10:59:42 +0000 (UTC) To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Subject: Re: [PATCH 6/9] hw/block/pflash_cfi02: Rename register_memory(true) as mode_read_array In-Reply-To: <20210309235028.912078-7-philmd@redhat.com> References: <20210309235028.912078-1-philmd@redhat.com> <20210309235028.912078-7-philmd@redhat.com> X-HGTTG: heart-of-gold From: David Edmondson Date: Wed, 10 Mar 2021 10:59:42 +0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: softfail client-ip=64.147.123.20; envelope-from=david.edmondson@oracle.com; helo=wout4-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Stephen Checkoway , qemu-block@nongnu.org, Max Reitz , Alistair Francis , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wednesday, 2021-03-10 at 00:50:25 +01, Philippe Mathieu-Daud=C3=A9 wrote: > The same pattern is used when setting the flash in READ_ARRAY mode: > - Set the state machine command to READ_ARRAY > - Reset the write_cycle counter > - Reset the memory region in ROMD > > Refactor the current code by extracting this pattern. > It is used three times: > > - When the timer expires and not in bypass mode > > - On a read access (on invalid command). > > - When the device is initialized. Here the ROMD mode is hidden > by the memory_region_init_rom_device() call. > > pflash_register_memory(rom_mode=3Dtrue) already sets the ROM device > in "read array" mode (from I/O device to ROM one). Explicit that > by renaming the function as pflash_mode_read_array(), adding > a trace event and resetting wcycle. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Edmondson Okay, I see that pflash_register_memory() was going to lose its second argument anyway, so perhaps no need to fix it in the previous patch. > --- > hw/block/pflash_cfi02.c | 18 +++++++++--------- > hw/block/trace-events | 1 + > 2 files changed, 10 insertions(+), 9 deletions(-) > > diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c > index 4efbae2f0c9..2ba77a0171b 100644 > --- a/hw/block/pflash_cfi02.c > +++ b/hw/block/pflash_cfi02.c > @@ -184,10 +184,13 @@ static void pflash_setup_mappings(PFlashCFI02 *pfl) > pfl->rom_mode =3D true; > } >=20=20 > -static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode) > +static void pflash_mode_read_array(PFlashCFI02 *pfl) > { > - memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode); > - pfl->rom_mode =3D rom_mode; > + trace_pflash_mode_read_array(); > + pfl->cmd =3D 0x00; > + pfl->wcycle =3D 0; > + pfl->rom_mode =3D true; > + memory_region_rom_device_set_romd(&pfl->orig_mem, true); > } >=20=20 > static size_t pflash_regions_count(PFlashCFI02 *pfl) > @@ -249,11 +252,10 @@ static void pflash_timer(void *opaque) > toggle_dq7(pfl); > if (pfl->bypass) { > pfl->wcycle =3D 2; > + pfl->cmd =3D 0; > } else { > - pflash_register_memory(pfl, 1); > - pfl->wcycle =3D 0; > + pflash_mode_read_array(pfl); > } > - pfl->cmd =3D 0; > } >=20=20 > /* > @@ -315,7 +317,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offs= et, unsigned int width) > /* Lazy reset to ROMD mode after a certain amount of read accesses */ > if (!pfl->rom_mode && pfl->wcycle =3D=3D 0 && > ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { > - pflash_register_memory(pfl, 1); > + pflash_mode_read_array(pfl); > } > offset &=3D pfl->chip_len - 1; > boff =3D offset & 0xFF; > @@ -933,8 +935,6 @@ static void pflash_cfi02_realize(DeviceState *dev, Er= ror **errp) > sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); >=20=20 > timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); > - pfl->wcycle =3D 0; > - pfl->cmd =3D 0; > pfl->status =3D 0; >=20=20 > pflash_cfi02_fill_cfi_table(pfl, nb_regions); > diff --git a/hw/block/trace-events b/hw/block/trace-events > index d32475c3989..f16d6e90cfd 100644 > --- a/hw/block/trace-events > +++ b/hw/block/trace-events > @@ -7,6 +7,7 @@ fdc_ioport_write(uint8_t reg, uint8_t value) "write reg 0= x%02x val 0x%02x" > # pflash_cfi01.c > # pflash_cfi02.c > pflash_reset(void) "reset" > +pflash_mode_read_array(void) "mode: read array" > pflash_timer_expired(uint8_t cmd) "command 0x%02x done" > pflash_io_read(uint64_t offset, unsigned size, uint32_t value, uint8_t c= md, uint8_t wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x cmd:0x%02x w= cycle:%u" > pflash_io_write(uint64_t offset, unsigned size, uint32_t value, uint8_t = wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x wcycle:%u" > --=20 > 2.26.2 dme. --=20 Ah, oh your hair is beautiful.