[Qemu-devel] ix64 target support

[Qemu-devel] ix64 target support

[Joe Batt]

I have a project that I'd like to code for 64 bit memory addressing (big
pointers).  I will eventually purchase 64 bit equipment, but I'd like to
do a feasibility test first.

qemu doesn't yet support a ix64 target.  How far are we from that?  Is
anyone working on it?  Is it as simple as implementing some extra
opcodes or are there fundamental issues?

I've implemented a simple sh2 emulator in a previous project; I
understand just a little of how qemu might work.  I may be able to help.

Thanks,
Joe

Re: [Qemu-devel] ix64 target support

[Johannes Schindelin]

Hi,

On Tue, 28 Sep 2004, Joe Batt wrote:

> qemu doesn't yet support a ix64 target.  How far are we from that?  Is
> anyone working on it?  Is it as simple as implementing some extra
> opcodes or are there fundamental issues?

There is nobody working on an ix64 target that I know of. BTW, you mean
x86_64, don't you? It should be as "easy" as implementing the opcodes.
AFAIK, the 64-bit mode of Opteron is not just a few extra opcodes, but
instead a whole new mode (like protected mode).  Also, you'd have to use a
few quirks to work with 64-bit numbers (for an example see op_smul_T1_T0
in target_sparc/op.c).

> I've implemented a simple sh2 emulator in a previous project; I
> understand just a little of how qemu might work.  I may be able to help.

This sounds like a very cool project to me. Unfortunately, I am quite busy
at work, and my pet right now is to make QEmu work on an IRIX machine, but
I sure would like to see that target one day.

Ciao,
Dscho

Re: [Qemu-devel] ix64 target support

[Karl Magdsick]

There is the ia64 architecture (Itanium) and the amd64 architecture
(Opteron, Athlon64, formerly known as x86_64).  (The Linux kernel
still uses the old architecture name, but some linux (??most??)
distributions have adopted the manufacturer's official name for the
architecture.)

I assume you're talking about amd64.

QEMU is capable of emulating PPC on x86, so the extra number of
registers on amd64 as opposed to x86 is not an issue.  Each 64 bit
register would, of course have to be treated as a pair of 32-bit
registers on 32-bit platforms, of course.

I have read that QEMU does not emulate the MMU (at least with some
target/host combinations), but you will probably need to emulate a
64-bit MMU on 32-bit platforms.  (Actually, I've read that current
amd64 chips actually use 40-bit addressing internally, so you only
need to emulate a 40-bit MMU.  I would personally not intentionally
emulate the limitations of the current batch of chips if the processor
family clearly is intended to go beyond these limitations in the
future.)

While we're on the subject of future plans for QEMU, I've read that
QEMU makes no attempts at optimal register allocation.  Are there
plans to change this in the future?  I've heard the arguments about
debugging, but I've heard that debuggers are refusing to debug the
translated code anyway.


Cheers,
-Karl

On Tue, 28 Sep 2004 11:52:05 -0500, Joe Batt <joe@soliddesign.net> wrote:
> I have a project that I'd like to code for 64 bit memory addressing (big
> pointers).  I will eventually purchase 64 bit equipment, but I'd like to
> do a feasibility test first.
> 
> qemu doesn't yet support a ix64 target.  How far are we from that?  Is
> anyone working on it?  Is it as simple as implementing some extra
> opcodes or are there fundamental issues?
> 
> I've implemented a simple sh2 emulator in a previous project; I
> understand just a little of how qemu might work.  I may be able to help.
> 
> Thanks,
> Joe
> 
> _______________________________________________
> Qemu-devel mailing list
> Qemu-devel@nongnu.org
> http://lists.nongnu.org/mailman/listinfo/qemu-devel
>

Re: [Qemu-devel] ix64 target support

[Joe Batt]

Actually, I'm just interested in 64bit address space, so any 64 bit chip
with a Linux distro would be great.  Would some old 64 bit risc chip
(Alhpa or HPPA) be easier?

I assume a lot of the interrupt and memory management can be adapted
from the x86 qemu code.  The SH2 was pretty simple in this respect and
there was only one "mode".  Anyone out there want to help me work though
some of this?

Volume 3 from 
http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,00.html
lists all the opcodes and what they do.  I started the SH2 emulator by
writing tests for each opcode, then the implementation from a document
like this.  Is there anything else I need to evaluate before I start
implementing opcodes?

Joe

On Tue, 2004-09-28 at 15:58, Karl Magdsick wrote:
> There is the ia64 architecture (Itanium) and the amd64 architecture
> (Opteron, Athlon64, formerly known as x86_64).  (The Linux kernel
> still uses the old architecture name, but some linux (??most??)
> distributions have adopted the manufacturer's official name for the
> architecture.)
> 
> I assume you're talking about amd64.
...

Re: [Qemu-devel] ix64 target support

[Kyle Hayes]

On Tuesday 28 September 2004 14:37, Joe Batt wrote:
> Actually, I'm just interested in 64bit address space, so any 64 bit chip
> with a Linux distro would be great.  Would some old 64 bit risc chip
> (Alhpa or HPPA) be easier?
>
> I assume a lot of the interrupt and memory management can be adapted
> from the x86 qemu code.  The SH2 was pretty simple in this respect and
> there was only one "mode".  Anyone out there want to help me work though
> some of this?

I think you'll find that the x86-64/AMD64 opcodes and behavior are very, 
very similar to the x86 specifications.  However, a lot of little things 
differ in system instructions (i.e. not user instructions).  The page 
translation tables are similar, but different for instance.  There are 
slightly more TLBs (not that this would make a difference to Qemu I 
think).

I believe that a large number of instructions are functionally identical to 
the older 32-bit versions.  Where differences exist, they tend to be 
across many instructions.  I.e. when doing 32-bit operations, the top 
32-bits of each 64-bit register is treated somewhat consistently (zeroed I 
think).

It will be the modes and how to handle things like traps (what to push on 
the stack etc.) that are going to be a bit nasty.  Not that the x86 chips 
are clean mind you :-)

> Volume 3 from
> http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,0
>0.html lists all the opcodes and what they do.  I started the SH2
> emulator by writing tests for each opcode, then the implementation from
> a document like this.  Is there anything else I need to evaluate before
> I start implementing opcodes?

I think I'd start by trying to see the differences between the instruction 
sets first.  Get a feel for it.  Remember that AMD64 is a 16/32/64-bit 
instruction set :-/

Best,
Kyle

[Qemu-devel] Re: ix64 target support

[Andi Kleen]

Kyle Hayes <kyle@silverbeach.net> writes:

> On Tuesday 28 September 2004 14:37, Joe Batt wrote:
>> Actually, I'm just interested in 64bit address space, so any 64 bit chip
>> with a Linux distro would be great.  Would some old 64 bit risc chip
>> (Alhpa or HPPA) be easier?
>>
>> I assume a lot of the interrupt and memory management can be adapted
>> from the x86 qemu code.  The SH2 was pretty simple in this respect and
>> there was only one "mode".  Anyone out there want to help me work though
>> some of this?
>
> I think you'll find that the x86-64/AMD64 opcodes and behavior are very, 
> very similar to the x86 specifications.  However, a lot of little things 
> differ in system instructions (i.e. not user instructions).  The page 

Actually not that many differences on the kernel side neither.

> translation tables are similar, but different for instance.  There are 

They are the same as IA32/PAE, just four levels and the third level
is a full page, not only four entries like on IA32.
But the entries in the page tables are the same.

> slightly more TLBs (not that this would make a difference to Qemu I 
> think).

Depends on the CPU. The Intel 64bit Xeons don't have that much
more TLBs.

> I believe that a large number of instructions are functionally identical to 
> the older 32-bit versions.  Where differences exist, they tend to be 
> across many instructions.  I.e. when doing 32-bit operations, the top 
> 32-bits of each 64-bit register is treated somewhat consistently (zeroed I 
> think).

Basically yes. And you have the 64bit override prefixes, which
allow to access the extended registers and use 64bit instructions.
It also has the RIP relative addressing mode there.

And there are two new instructions: movabs (to load 64bit constants) 
and swapgs for the kernel.

> It will be the modes and how to handle things like traps (what to push on 
> the stack etc.) that are going to be a bit nasty.  Not that the x86 chips 
> are clean mind you :-)

It's not that different. The main difference is that all the values
in the stack frame are 8 bytes, not 4 bytes. 

There are some other differences in the stack frames, but they 
should be relatively easy to handle.

You'll have to handle compat mode for a full system emulation 
(32bit programs on 64bit kernel), which can be a bit tricky.

Overall it should be relatively straight forward to convert it over.
Someone did the port of Bochs also in a short time.

>> Volume 3 from
>> http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,0
>>0.html lists all the opcodes and what they do.  I started the SH2
>> emulator by writing tests for each opcode, then the implementation from
>> a document like this.  Is there anything else I need to evaluate before
>> I start implementing opcodes?
>
> I think I'd start by trying to see the differences between the instruction 
> sets first.  Get a feel for it.  Remember that AMD64 is a 16/32/64-bit 
> instruction set :-/

There is an older document from AMD that just lists the differences
from 32bit to 64bit (not sure if it's still available, they switched
to full manuals some time ago) Intel also has a similar document on
their website that documents the delta from IA32 to x86-64 in
their flavour of AMD64 (which is practically identical to AMD's except
that they call it EM64T)

-Andi

Re: [Qemu-devel] ix64 target support

[Paul Brook]

On Tuesday 28 September 2004 22:37, Joe Batt wrote:
> Actually, I'm just interested in 64bit address space, so any 64 bit chip
> with a Linux distro would be great.  Would some old 64 bit risc chip
> (Alhpa or HPPA) be easier?
>
> I assume a lot of the interrupt and memory management can be adapted
> from the x86 qemu code.  The SH2 was pretty simple in this respect and
> there was only one "mode".  Anyone out there want to help me work though
> some of this?
>
> Volume 3 from
> http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,00.h
>tml lists all the opcodes and what they do.  I started the SH2 emulator by
> writing tests for each opcode, then the implementation from a document like
> this.  Is there anything else I need to evaluate before I start
> implementing opcodes?

You'll probably also need to implement SSE+SSE2. Certainly the linux amd64 ABI 
uses these.

Paul

[Qemu-devel] Re: ix64 target support

[Blue Swirl]

Hi,

One challenging project could be adding 64-bit instructions to Sparc, there 
are not too many of them. and the architecture was designed with scalability 
in mind. On the negative side, 32-bit Sparc system target is not functional 
yet and address space size could be a problem, as with any 64-bit CPUs.

PPC specs include both 32-bit and 64-bit implementations and the Qemu 
emulation works. The architecture is much more complex than Sparc, though. 
MIPS is one option with both 32 and 64-bit CPUs, but there isn't anything in 
Qemu side.

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