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From: Andreas Schwab <schwab@suse.de>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: laurent@vivier.eu,  qemu-devel@nongnu.org
Subject: Re: [PATCH] linux-user: Add /proc/cpuinfo handler for RISC-V
Date: Tue, 02 May 2023 17:47:52 +0200	[thread overview]
Message-ID: <mvmttwu4tw7.fsf@suse.de> (raw)
In-Reply-To: <mhng-387c6a65-31c0-4fcd-bf29-bd798c2a47f6@palmer-ri-x1c9> (Palmer Dabbelt's message of "Tue, 02 May 2023 07:58:03 -0700 (PDT)")

On Mai 02 2023, Palmer Dabbelt wrote:

> On Tue, 02 May 2023 06:44:00 PDT (-0700), schwab@suse.de wrote:
>> Signed-off-by: Andreas Schwab <schwab@suse.de>
>> ---
>>  linux-user/syscall.c | 30 ++++++++++++++++++++++++++++--
>>  1 file changed, 28 insertions(+), 2 deletions(-)
>>
>> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
>> index 69f740ff98..c72456a34b 100644
>> --- a/linux-user/syscall.c
>> +++ b/linux-user/syscall.c
>> @@ -8231,7 +8231,8 @@ void target_exception_dump(CPUArchState *env, const char *fmt, int code)
>>  }
>>
>>  #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
>> -    defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
>> +    defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
>> +    defined(TARGET_RISCV)
>>  static int is_proc(const char *filename, const char *entry)
>>  {
>>      return strcmp(filename, entry) == 0;
>> @@ -8309,6 +8310,31 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
>>  }
>>  #endif
>>
>> +#if defined(TARGET_RISCV)
>> +static int open_cpuinfo(CPUArchState *cpu_env, int fd)
>> +{
>> +    int i, num_cpus;
>> +
>> +    num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
>> +    for (i = 0; i < num_cpus; i++) {
>> +        dprintf(fd, "processor\t: %d\n", i);
>> +        dprintf(fd, "hart\t\t: %d\n", i);
>> +#if defined(TARGET_RISCV32)
>> +        dprintf(fd, "isa\t\t: rv32imafdc\n");
>> +        dprintf(fd, "mmu\t\t: sv32\n");
>> +#endif
>> +#if defined(TARGET_RISCV64)
>> +        dprintf(fd, "isa\t\t: rv64imafdc\n");
>> +        dprintf(fd, "mmu\t\t: sv57\n");
>
> Unless I'm misunderstanding something, we've got support for both non-sv57
> system (via sv* CPU properties)

The mmu type is not available in linux-user emulation.  This just
matches the default the system emulation would use.

> and non-GC systems (also via CPU properties).

None of the currently defined cpus are non-GC cpus (except sifive_e, but
that is not suitable for user-space anyway), and there doesn't appear to
be any properties defined for changing the supported extensions.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."


  reply	other threads:[~2023-05-02 15:49 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-02 13:44 [PATCH] linux-user: Add /proc/cpuinfo handler for RISC-V Andreas Schwab
2023-05-02 14:58 ` Palmer Dabbelt
2023-05-02 15:47   ` Andreas Schwab [this message]
2023-05-03 11:13     ` Andreas Schwab
2023-05-03 14:57       ` Palmer Dabbelt

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