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[79.129.180.152]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cf270fc0a8sm2287718f8f.7.2025.08.29.00.40.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 00:40:11 -0700 (PDT) Date: Fri, 29 Aug 2025 10:36:29 +0300 From: Manos Pitsidianakis To: qemu-devel@nongnu.org, Richard Henderson Cc: qemu-arm@nongnu.org Subject: Re: [PATCH 18/61] target/arm: Remove cp argument to ENCODE_AA64_CP_REG User-Agent: meli/0.8.12 References: <20250827010453.4059782-1-richard.henderson@linaro.org> <20250827010453.4059782-23-richard.henderson@linaro.org> In-Reply-To: <20250827010453.4059782-23-richard.henderson@linaro.org> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 27 Aug 2025 04:04, Richard Henderson wrote: >All invocations were required to pass the same value, >CP_REG_ARM64_SYSREG_CP. Bake that in to the result directly. >Remove CP_REG_ARM64_SYSREG_CP as unused. > >Signed-off-by: Richard Henderson >--- Reviewed-by: Manos Pitsidianakis > target/arm/cpregs.h | 5 ++--- > target/arm/kvm-consts.h | 3 --- > target/arm/helper.c | 11 +++++------ > target/arm/hvf/hvf.c | 3 +-- > target/arm/tcg/translate-a64.c | 6 ++---- > 5 files changed, 10 insertions(+), 18 deletions(-) > >diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h >index 7ebe404163..95b0b9c78e 100644 >--- a/target/arm/cpregs.h >+++ b/target/arm/cpregs.h >@@ -187,9 +187,8 @@ enum { > ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ > ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) > >-#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ >- (CP_REG_AA64_MASK | \ >- ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ >+#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \ >+ (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ > ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ > ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ > ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ >diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h >index fdb305eea1..54ae5da7ce 100644 >--- a/target/arm/kvm-consts.h >+++ b/target/arm/kvm-consts.h >@@ -160,9 +160,6 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53); > #define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 > #define CP_REG_ARM64_SYSREG_OP2_SHIFT 0 > >-/* No kernel define but it's useful to QEMU */ >-#define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT) >- > MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64); > MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK); > MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT); >diff --git a/target/arm/helper.c b/target/arm/helper.c >index 268cad905f..93cae888e2 100644 >--- a/target/arm/helper.c >+++ b/target/arm/helper.c >@@ -4527,7 +4527,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) > }; > > #define K(op0, op1, crn, crm, op2) \ >- ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) >+ ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) > > static const struct E2HAlias aliases[] = { > { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), >@@ -7297,10 +7297,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, > * in their AArch64 view (the .cp value may be non-zero for the > * benefit of the AArch32 view). > */ >- if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { >- cp = CP_REG_ARM64_SYSREG_CP; >- } >- key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); >+ assert(cp == 0 || r->state == ARM_CP_STATE_BOTH); >+ cp = 0; >+ key = ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2); > break; > default: > g_assert_not_reached(); >@@ -7525,7 +7524,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) > } > break; > case ARM_CP_STATE_AA64: >- assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); >+ assert(r->cp == 0); > break; > default: > g_assert_not_reached(); >diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c >index 9dffa99ed1..af03fc7fc1 100644 >--- a/target/arm/hvf/hvf.c >+++ b/target/arm/hvf/hvf.c >@@ -1124,8 +1124,7 @@ static bool is_id_sysreg(uint32_t reg) > > static uint32_t hvf_reg2cp_reg(uint32_t reg) > { >- return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, >- (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, >+ return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, > (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, > (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, > (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, >diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c >index dbf47595db..743c5a10e1 100644 >--- a/target/arm/tcg/translate-a64.c >+++ b/target/arm/tcg/translate-a64.c >@@ -2466,8 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread, > unsigned int op0, unsigned int op1, unsigned int op2, > unsigned int crn, unsigned int crm, unsigned int rt) > { >- uint32_t key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, >- crn, crm, op0, op1, op2); >+ uint32_t key = ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2); > const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key); > bool need_exit_tb = false; > bool nv_trap_to_el2 = false; >@@ -2603,8 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread, > * We don't use the EL1 register's access function, and > * fine-grained-traps on EL1 also do not apply here. > */ >- key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, >- crn, crm, op0, 0, op2); >+ key = ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2); > ri = get_arm_cp_reginfo(s->cp_regs, key); > assert(ri); > assert(cp_access_ok(s->current_el, ri, isread)); >-- >2.43.0 > >